Arm Limited

Advanced Risc Machines Limited

Other

David Vivian Jaggar

David Terrence Matheny

Christopher Neal Hinds

David James Seal

Simon James Glass

William Adam Hohl

Guy Larri

Matthew Paul Elwood

James Stroman Hall

William Henry Oldfield

The present invention provides a data processing apparatus and method for predicting instructions in a data processing apparatus. The data processing apparatus comprises a processor core for executing instructions from any of a plurality of instruction sets, and a prefetch unit for prefetching instructions from a memory prior to sending those instructions to the processor core for execution. Further, prediction logic is used to predict which instructions should be prefetched by the prefetch unit, the prediction logic being arranged to review a prefetched instruction to predict whether execution of that prefetched instruction will cause a change in instruction flow, and if so to indicate to the prefetch unit an address within the memory from which a next instruction should be retrieved. Furthermore, in accordance with the present invention, the prediction logic is arranged to predict whether the prefetched instruction will additionally cause a change in instruction set, and if so to cause an instruction set identification signal to be generated for sending to the processor core to indicate the instruction set to which the next instruction belongs. This provides a particularly efficient technique for enabling the processor core to switch between different instruction sets.

Prediction of instructions in a data processing apparatus

Data processing apparatus and method for applying floating-point operations to first, second and third operands

Apparatus for processing data is provided, said apparatus comprising: a main processor responsive to main processor instructions within a stream of instructions input to said main processor to perform main processor operations; a coprocessor coupled to said main processor via a coprocessor interface CP and responsive to coprocessor instructions MCR, MRC within said stream of instructions to perform coprocessor operations; wherein said coprocessor is a debug coprocessor operable to at least partially control generation of diagnostic data for debugging said apparatus for processing data and said coprocessor instructions are debug coprocessor instructions that control operation of said debug coprocessor. Using a debug mechanism in the form of a debug coprocessor reduces the impact of the debug mechanism upon normal operation.

Debug mechanism for data processing systems

Data processing apparatus and method for performing multiply-accumulate operations

Apparatus for processing data is provided, said apparatus comprising: a main processor ; an instruction transfer register ITR for holding a data processing instruction and accessible via a first serial scan chain SC ; a data transfer register DTR for holding a data value and accessible via a second serial scan chain SC ; debug logic for controlling said main processor , said instruction transfer register ITR and said data transfer register DTR such that a data processing instruction held within said instruction transfer register ITR is passed a plurality of times to said main processor for execution upon a sequence of data values scanned into or from said data transfer register via said second serial scan chain. In this way operational speed of the debug mode is increased since the data processing instruction only needs to be transferred once.

Executing multiple debug instructions

Apparatus for processing data is provided, said apparatus comprising: a main processor,driven by a main processor clock signal clk at a main processor clock frequency; debug logic,at least a portion,of which is driven by a debug clock signal tck at a debug clock frequency, said debug clock frequency being different to said main processor clock frequency and said main processor clock signal clk being asynchronous with said debug clock signal tck; and an instruction transfer register ITR into which a data processing instruction may be transferred by said debug logic,and from which said data processing instruction may be read by said main processor,wherein when switched from a normal mode to a debug mode said main processor,continues to be driven by said main processor clock signal clk executing no-operation instructions until a data processing instruction is present within said instruction transfer register ITR and said debug logic,triggers said main processor to read and execute said data processing instruction whilst still driven by said main processor clock signal clk. This arrangement allows debug instructions to be executed at full speed whilst avoiding the need to switch clock speeds and provide a synchronisation mechanism.

Executing debug instructions

A floating point unit is provided with a register bank comprising 32 registers that may be used as either vector registers of scalar registers. A data processing instruction includes at least one register specifying field pointing to a register containing a data value to be used in that operation. An increase in the instruction bit space available to encode more opcodes or to allow for more registers is provided by encoding whether a register is to be treated as a vector or a scalar within the register field itself. Further, the register field for one register of the instruction may encode whether another register is a vector or a scalar. The registers can be initially accessed using the values within the register fields of the instruction independently of the opcode allowing for easier decode.

Apparatus and method for processing data having a mixed vector/scalar register file

A data processing system having a main processor and a coprocessor. The main processor responsds to coprocessor instructions within its instruction stream by issuing the coprocessor instructions upon a coprocessor bus and detecting if the coprocessor accepts them by returning an accept signal. The coprocessor instructions include a coprocessor number and the coprocessor checks this number to see if it matches its own number(s) to determine whether or not it should accept the coprocessor instruction. A data type field within the coprocessor number in the coprocessor instruction also serves to specify one of multiple data types to be used in the coprocessor operation; particular coprocessors can interpret this part of the coprocessor number to determine data type. If the coprocessor supports multiple data types, then it has multiple coprocessor numbers for which it will issue accept signals and then uses the data type field to control the data type used. If a coprocessor does not support a particular data type then it will not issue an accept signal for coprocessor instructions that specify that data type. The main processor can then use emulation code to provide support for that coprocessor instruction.

Coprocessor opcode division by data type

A data processing apparatus and method is provided, the apparatus comprising an execution unit having a plurality of pipelined stages for executing instructions, such that a maximum of 'n' instructions can be being executed simultaneously within the execution unit. Further, a set of at least 'n' logical exception registers are provided, each exception register being capable of storing a number of exception attributes associated with an instruction for which an exception has been detected during execution by the execution unit. In the event of an exception being detected during execution of a first instruction, the execution unit is arranged to: (i) store in a first of said exception registers said exception attributes associated with said first instruction; and (ii) to continue executing any remaining instructions already in the pipelined stages at the time the exception was detected. The execution unit is further arranged to store in said exception registers the exception attributes associated with any of the remaining instructions for which an exception is detected during execution, whereby the exception attributes stored in the exception registers can be provided to an exception processing tool for use in recovering from any exceptions occurring during processing of said first instruction and said remaining instructions. By this approach, when the exception processing tool is invoked, then it can deal with any exceptions arising from the instructions executed by the pipeline, and the data processing apparatus can then continue with the next instruction, without the need to re-execute any of the instructions that were in the pipeline at the time the first exception was detected.

Handling exceptions in a pipelined data processing apparatus

A floating point unit having a register bank containing a plurality of registers supports vector operations that execute a specified operation a plurality of times upon a sequence of data values form different registers. The register bank is divided into subsets and with the sequence of registers used in a vector operation wrapping within a subset. The subsets comprise disjoint, contiguous ranges of register numbers. The wrapping within ranges allows compact code and efficient to be provided for performing DSP operations, such as FIR filtering and matrix transformations.

Recirculating register file

A floating point unit is described that performs addition operations. An adder 16 within the floating point unit receives a first input and a second input to generate a sum. This sum is subject to subsequent normalization by a normalizer 60 and rounding by an incrementer 64. If an operation is performed that is immediately followed by an addition operation using the result of the preceding operation, then the normalized but unrounded sum is fed back to the adder 16 together with an indication of its rounding requirement. This rounding requirement can be performed by the adder 16 in parallel with the execution of the following addition by using the carry-in bit of the adder 16 to apply any increment required to rounding of the preceding result.

Round increment in an adder circuit

A floating point unit 10 provides a multiply-accumulate operation to determine a result B+(A*C). The multiplier 20 takes several processing cycles to determine the product (A*C). Whilst the multiplier 20 and its subsequent carry-save-adder 26 operate, an aligned value B' of the addend B is generated by an alignment-shifter 34. The aligned-addend B' may only partially overlap with the product (A*C) to which it is to be added using an adder 44. Any high-order-portion HOP of the aligned-addend B' that does not overlap with the product (A*C) must be subsequently concatenated with the output of the adder 44 that sums the product (A*C) with the overlapping portion of the aligned-addend B'. If the sum performed by the adder 44 generates a carry then it is an incremented version IHOP of the high-order-portion that should be concatenated with the output of the adder 44. This incremented-high-order-portion is generated by the adder 44 during otherwise idle processing cycles present due to the multiplier 20 operating over multiple cycles.

Floating point multiply-accumulate unit

A data processing system is provided including an arithmetic logic unit 20, 22, 24 receiving input operands from M X-bit registers to produce output data words stored within N Y-bit registers, where M/N=3, 8.ltoreq.Y-X.ltoreq.16 and 3X=2Y. This arrangement is particularly suited for digital signal processing and in situations where each input operand is used a plurality of times before a new input operand is loaded in its place in a register.

Data processing apparatus registers

Execution of data processing instructions

A data processing system having a plurality of registers 10 and an arithmetic logic unit 20, 22, 24 is responsive to program instruction words. At least one program instruction word includes a destination register bit field &lt;dest&gt; specifying a destination register of a result data word and a destination register write disable flag for disabling writing of that result data word to the destination register.

Growing community of inventors

Cherry Hinton, United Kingdom

David Vivian Jaggar