Stmicroelectronics S.r.l.

Stmicroelectronics Design and Application S.r.o.

David Vincenzoni

Samuele Raffaelli

Ignazio Salvatore Bellomo

Luca Giussani

Ales Loidl

In an embodiment, a circuit includes cascaded delay units arranged in a chain, each delay unit having an input-to-output delay time, wherein a first delay unit in the chain is configured to receive an input signal for propagating along the delay units in the chain, logic circuitry coupled to delay units in the chain, the logic circuitry configured to generate a clock signal as a logic combination of signals input to and output from the delay units in the chain and feedback circuitry configured to supply to the first delay unit in the chain a feedback signal, the feedback circuitry including a first feedback signal path from a last delay unit in the chain to the first delay unit in the chain and a second feedback signal path from an intermediate delay unit in the chain to the first delay unit in the chain, the intermediate delay unit arranged between the first delay unit in the chain and the last delay unit in the chain.

Clock generator circuit, corresponding device and method

A clock recovery circuit comprises an input node receiving a data signal having a data rate, and a digital oscillator producing a local clock signal with a frequency higher than the data rate. A counter clocked by the local clock signal has its count value sampled and reset at the rising and falling edges of the data signal, and a storage block coupled to the counter stores a count value that is updated in response to the current sampled count value of the counter lying in an update range between lower and upper bounds. A threshold value set is produced as a function of the updated count value stored in the storage block. Sampling circuitry receives and samples the data signal, and provides a sampled version of the data signal in response to the count value of the counter reaching any of the threshold values.

Clock recovery circuit, corresponding device and method

A method can be used to test an electronic circuit. The method includes applying a test stimulus signal to the input node, collecting a sequence of N-bit digital test data at the output port. The N-bit digital test data is determined by the test stimulus signal applied to the input node. The method also includes applying N-bit to R-bit lossless compression to the N-bit digital test data to obtain R-bit compressed test data (R is less than N) and making the R-bit compressed test data available in parallel format over R output pins of the circuit.

Method of testing electronic circuits and corresponding circuit

A circuit includes a multiplier, an adder, a first result register and a second result register coupled to outputs of the multiplier and the adder, respectively. The circuit further includes: a first selection unit configured to selectively provide, to the multiplier and in response to a first control signal, a first value from a first plurality of values; and a second selection unit configured to selectively provide, to the multiplier and in response to a second control signal, a second value from a second plurality of values. The circuit also includes: a third selection unit configured to selectively provide, to the adder and in response to a third control signal, a third value from a third plurality of values; and a fourth selection unit configured to selectively provide, to the adder and in response to a fourth control signal, a fourth value from a fourth plurality of values.

Circuit for performing a multiply-and-accumulate operation

A state machine for generating signals configured for generating different signals according to the current state of the machine. The state machine is configured to change state both as a function of an internal timer and as a function of signals representative of events external to the state machine.

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Usmate Velate, Italy

David Vincenzoni