IP Reservoir, LLC

Exegy Incorporated

Washington University

David Vincent Schuehler

David E Taylor

Scott Parsons

Roger Dean Chamberlain

Mark Allen Franklin

Andy Young Lee

John W Lockwood

Todd Alan Strader

Ryan L Eder

Systems and methods are disclosed herein that compute trading signals with low latency and high throughput using highly parallelized compute resources such as integrated circuits, reconfigurable logic devices, graphics processor units (GPUs), multi-core general purpose processors, and/or chip multi-processors (CMPs). The trading signals can be summarized over time durations to create derived summaries of the trading signals. These derived summaries can be communicated with one or more data consumers.

Methods and systems for generating derived summaries of trading signals

Systems and methods are disclosed herein that compute trading signals with low latency and high throughput using highly parallelized compute resources such as integrated circuits, reconfigurable logic devices, graphics processor units (GPUs), multi-core general purpose processors, and/or chip multi-processors (CMPs). For example, an estimation that estimates a quote price duration for a quote on a financial instrument can be generated from streaming financial market data.

Methods and systems for low latency generation and distribution of quote price duration estimates

Systems and methods are disclosed herein that compute trading signals with low latency and high throughput using highly parallelized compute resources such as integrated circuits, reconfigurable logic devices, graphics processor units (GPUs), multi-core general purpose processors, and/or chip multi-processors (CMPs). For example, a liquidity estimation that estimates an amount of hidden liquidity for a financial instrument can be generated from streaming financial market data.

Methods and systems for low latency generation and distribution of hidden liquidity size estimates

Systems and method are disclosed for distributed data processing across multiple compute resources. For example, the system may comprise a ticker plant configured to receive streaming financial market data events from a plurality of feeds, the events comprising financial market data pertaining to financial instruments. The ticker plant may comprise a processor, an FPGA, and a shared memory, wherein the shared memory is shared between the processor and the FPGA, wherein the processor is configured to execute software to manage a flow of financial market data derived from the streaming events between the processor and the FPGA via DMA transfers of the financial market data between the processor and the FPGA via the shared memory, and wherein the FPGA comprises reconfigurable hardware that is configured to perform processing operations on the financial market data to generate processed financial market data for delivery to data consumers.

System and method for distributed data processing across multiple compute resources

Systems and methods are disclosed herein that compute trading signals with low latency and high throughput using highly parallelized compute resources such as integrated circuits, reconfigurable logic devices, graphics processor units (GPUs), multi-core general purpose processors, and/or chip multi-processors (CMPs). For example, an estimation that estimates a quote price direction for a quote on a financial instrument can be generated from streaming financial market data.

Methods and systems for low latency generation and distribution of quote price direction estimates

Systems and methods are disclosed herein that compute trading signals with low latency and high throughput using highly parallelized compute resources such as integrated circuits, reconfigurable logic devices, graphics processor units (GPUs), multi-core general purpose processors, and/or chip multi-processors (CMPs). For example, a liquidity indicator that indicates a presence of a hidden order for a financial instrument can be generated based on processing of streaming financial market data that operates to detect the existence of hidden orders within the financial market data.

Methods and systems for low latency generation and distribution of hidden liquidity indicators

Systems and methods are disclosed herein that compute trading signals with low latency and high throughput using highly parallelized compute resources such as integrated circuits, reconfigurable logic devices, graphics processor units (GPUs), multi-core general purpose processors, and/or chip multi-processors (CMPs). Examples of trading signals that can be computed in this fashion include a liquidity indicator that indicates a presence of a reserve order for a financial instrument, a liquidity estimation that estimates an amount of hidden liquidity for a financial instrument, a quote price stability estimation that estimates a duration of time for which a price quote for a financial instrument will be valid, and/or a quote price direction estimation that estimates whether the price in a next quote for a financial instrument will be higher or lower than the price for that financial instrument in the current quote.

Methods and systems for low latency generation and distribution of trading signals from financial market data

Systems and methods are disclosed for routing of streaming data as between multiple compute resources. For example, the system may comprise a processor, a field programmable gate array (FPGA), a shared memory that is shared by a user space of an operating system for the processor and the FPGA, a network protocol stack, and driver code for execution by the processor. The driver code can be configured to (1) make the received streaming data available to a user mode software application for processing, (2) make data stored in the shared memory available to the FPGA via DMA transfers of data from the shared memory into the FPGA for processing thereby, (3) receive a stream of processed data from the FPGA, and (4) provide the received processed data to the network protocol stack for delivery to one or more data consumers. The shared memory can be accessible to the user mode for storing data produced by the user mode software application as a result of processing performed by the user mode software application on the streaming data received by the network protocol stack.

System and method for routing of streaming data as between multiple compute resources

Systems and methods are disclosed for routing of streaming data as between multiple compute resources. For example, the system may comprise a processor, a field programmable gate array (FPGA), a shared memory that is shared by a user space of an operating system for the processor and the FPGA, a network protocol stack, and driver code for execution by the processor. The driver code can be configured to (1) copy the streaming data received by the network protocol stack into the shared memory, (2) facilitate DMA transfers of the streaming data from the shared memory into the FPGA for processing thereby, (3) receive a stream of processed data from the FPGA, and (4) deliver the received processed data to the network protocol stack for delivery to one or more data consumers.

Systems and methods are disclosed for fast track routing of streaming data as between multiple compute resources. For example, the system may comprise a first processor, a second processor, a shared memory that is mapped into a kernel and user space of an operating system for the processor, a network protocol stack, and driver code for execution within the kernel space of the operating system while the operating system is in the kernel mode. The driver code can be configured to (1) maintain a kernel level interface into the network protocol stack, (2) copy the streaming data from the network protocol stack into the shared memory, wherein the copy operation is performed by the driver code without the operating system transitioning to the user mode, and (3) facilitate DMA transfers of data from the shared memory into the second processor for processing thereby.

Fast track routing of streaming data as between multiple compute resources

A high speed apparatus and method for processing a plurality of financial market data messages are disclosed. With respect to an exemplary embodiment, a reconfigurable logic device is employed to generate a plurality of financial market data messages from a plurality of the data fields, each generated message having a specified message format.

High speed processing of financial information using FPGA devices

Systems and methods are disclosed for fast track routing of streaming data as between multiple compute resources. For example, the system may comprise a processor, reconfigurable logic device, a shared memory that is mapped into a kernel and user space of an operating system for the processor, a network protocol stack, and driver code for execution within the kernel space of the operating system while the operating system is in the kernel mode. The driver code can be configured to (1) maintain a kernel level interface into the network protocol stack, (2) copy the streaming data from the network protocol stack into the shared memory, wherein the copy operation is performed by the driver code without the operating system transitioning to the user mode, and (3) facilitate DMA transfers of data from the shared memory into the reconfigurable logic device for processing thereby.

Fast track routing of streaming data using FPGA devices

A high speed apparatus and method for processing financial instrument order books are disclosed. With respect to an exemplary embodiment, a reconfigurable logic device is employed to synthesize quote events associated with a plurality of financial instruments from a financial market data feed.

A high speed apparatus and method for processing a plurality of financial market data messages are disclosed. With respect to an exemplary embodiment, a reconfigurable logic device is employed to map the symbols present in the financial market data messages to another symbology.

Methods and systems for processing financial market data using a reconfigurable logic device are disclosed. Various operations such as volume weighted average price (VWAP) operations can be performed on the financial market data using firmware logic deployed on the reconfigurable logic device to accelerate the speed of processing.

Growing community of inventors

St. Louis, MO, United States of America

David Vincent Schuehler