Agilent Technologies, Inc.

David Victor Pietromonaco

Ralph H Lanham

An apparatus and method for shortening the read operation (typically the longest operation) in a destructive read memory is disclosed. The rewrite step is separated from the read operation and delayed to the subsequent clock cycle. A FeRAM memory cell having two ports is needed so that consecutive operations do not conflict with each other. A read operation is initiated through a first port in a first clock cycle. In the subsequent clock cycle, the rewrite finishes through the first port. The next operation utilizes the second port, without conflicting with the rewrite process. By alternating ports used in each clock cycle, the rewrite step is hidden in the subsequent clock cycle to shorten the read operation. In an alternate method, all read operations are initiated through one port, while the second port is reserved exclusively for write operations and rewrites.

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Sunnyvale, CA, United States of America

David Victor Pietromonaco