Arm Limited

Tokyo Electron Limited

David Victor Pietromonaco

Amit Chhabra

Lars W Liebmann

Daniel Chanemougame

Jeffrey Smith

Xiaoqing Xu

Brian Cline

Paul Gutwin

Paul T Gutwin

Krishnendra Nathella

Divya Madapusi Srinivas Prasad

According to one implementation of the present disclosure, a cache memory includes: a plurality of cache-lines, wherein each row of cache-lines comprises: tag bits of a tag-random access memory (tag-RAM); data bits of a data-random access memory (data-RAM), and a single set of retention bits corresponding to the tag-RAM. According to one implementation of the present disclosure, a method includes: sampling a single set of retention bits of a cache-line of a cache memory, where the cache-line comprises the single set of retention bits, tag-RAM and data-RAM, and where at least the single set of retention bits comprise eDRAM bitcells; and performing a refresh cycle of at least the data-RAM corresponding to the tag-RAM based on the sampled single set of retention bits.

Systems, devices, and methods of cache memory

A semiconductor device includes a first pair of transistors over a substrate. The first pair of transistors includes a first transistor having a first gate structure over the substrate and a second transistor having a second gate structure stacked over the first transistor. A second pair of transistors is stacked over the first pair of transistors, resulting in a vertical stack perpendicular to a working surface of the substrate. The second pair of transistors includes a third transistor having a third gate structure stacked over the second transistor and a fourth transistor having a fourth gate structure stacked over the third transistor. The third gate structure extends from a central region of the vertical stack to a first side of the vertical stack. The second gate structure and the fourth gate structure extend from the central region to a second side of the vertical stack opposite the first side.

Interdigitated device stack

Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a lower semiconductor device tier, and a lower signal wiring structure electrically connected to the lower semiconductor device tier. The multi-tier semiconductor structure can further include a primary power delivery network (PDN) structure disposed over the lower semiconductor device tier and the lower signal wiring structure and electrically connected to the lower semiconductor device tier. The multi-tier semiconductor structure can further include an upper semiconductor device tier disposed over and electrically connected the first PDN structure, and an upper signal wiring structure disposed over the primary PDN structure and electrically connected to the upper semiconductor device tier.

Inter-tier power delivery network (PDN) for dense gate-on-gate 3D logic integration

Various implementations described herein relate to a device with a multi-transistor logic structure for use in memory architecture. In some applications, the multi-transistor logic structure may have a pair of P-type transistors that are arranged in a P-over-P multi-transistor stack. In other applications, the multi-transistor logic structure may have a pair of N-type transistors that are arranged in an N-over-N multi-transistor stack.

Memory architecture

Various implementations described herein relate to a method for manufacturing, or causing to be manufactured, multiple devices packaged within a single semiconductor die. The multiple devices may have first devices that are arranged in a first multi-transistor stack with a first P-N configuration. The multiple devices may have second devices that are arranged in a second multi-transistor stack with a second P-N configuration that is different than the first P-N configuration.

Multi-transistor stack architecture in a single vertical stack

Various implementations described herein are related to a device having multiple transistors in a single stack arranged as a cross-coupled bitcell latch. Also, the multiple transistors may be disposed in a multi-transistor stack configuration that is formed within a single monolithic semiconductor die. In some implementations, the multiple transistors may be arranged as a bitcell for single-port memory applications.

Multi-transistor stack bitcell architecture

In one implementation, a circuit includes: a comparator; a shift register chain coupled to the comparator; and one or more converters coupled to respective shift registers of the shift register chain, wherein the one or more converters are configured to convert a source of current from a first voltage to a second voltage, and wherein the circuit is configured to selectively transmit an output signal to the one or more converters. In one implementation, the circuit is configured to selectively control modulation for the one or more converters.

Control circuitry and methods for converters

Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first power delivery network (PDN) structure, and a first semiconductor device tier disposed over and electrically connected to the first PDN structure. The multi-tier semiconductor structure can further include a signal wiring tier disposed over and electrically connected to the first semiconductor device tier, a second semiconductor device tier disposed over and electrically connected to the signal wiring tier, and a second PDN structure disposed over and electrically connected to the second semiconductor device tier. The multi-tier semiconductor structure can further include a through-silicon via (TSV) structure electrically connected to the signal wiring tier, wherein the TSV structure penetrates the second PDN structure.

Multi-tier backside power delivery network for dense gate-on-gate 3D logic

Method of forming multi-stack transistors in a single semiconductor die

An electric motor is disclosed having a detachable stator tooth. In some implementations, coil windings of the electric motor may be coupled to one or more drivers independently of other coil windings. A method of repairing and manufacturing an electric motor having a detachable stator tooth is also disclosed.

Method for manufacture of electric motor

An electric motor may comprise a rotor and a stator comprising rotor and stator teeth, respectively. A non-uniform angular spacing or grouping of rotor teeth may facilitate desired rotational speeds of the rotor.

Grouped tooth electric motor

Apparatus and methods are provided for operating an electric motor, comprising selectively energising the coils of a stator having a plurality of stator teeth, each stator tooth having a said coil mounted thereon. The stator coils of a subset of the stator teeth are energised during a given time period to attract a corresponding rotor tooth into alignment with each of the stator teeth in the subset over the given time period. The stator coil of at least one stator tooth in the subset is energised during a portion of the given time period before the at least one stator tooth overlaps the corresponding rotor tooth.

Method and apparatus for operating an electric motor

An electrical motor comprising multiple inductive coils, and a method for using same, is disclosed. The inductive coils may be configured to conduct current bi-directionally. Terminals of the inductive coils may be coupled to a common node on a power bus coupled to a power supply. Current flowing in a first inductive coil from the power bus may be largely offset by current returned to the power bus from a second inductive coil.

Motor driver and a method of operating thereof

An electric motor may comprise a rotor and a stator comprising rotor and stator teeth, respectively. A non-uniform angular spacing or grouping of rotor teeth may facilitate desired rotational speeds of the rotor. In an embodiment, such non-uniform angular spacing may be such that for at least a subset of the rotor teeth comprising a first, second, and third rotor tooth, an angular spacing between the first and the second rotor teeth is at least twice an angular spacing between the second and the third rotor teeth.

Growing community of inventors

Cupertino, CA, United States of America

David Victor Pietromonaco