Broadcom Corporation

David Vetea Greig

Christopher Pasqualino

Erlend Olson

Rick Berard

A receiver includes clock termination circuitry that is capable of applying either a terminating impedance or a high impedance to a transmission path that carries a clock signal. When multiple of these receivers are used to service data links that share a clock signal, one of the clock termination circuits applies the terminating impedance to the transmission path that carries the clock signal while the other clock termination circuit(s) applies a high impedance to the transmission path. The receiver also includes a plurality of high rate serial bit stream buffers and a clock signal buffer along with the clock termination circuitry. In other embodiments, the receiver includes a deserializer and may include a controller. The receiver may service a dual link Digital Visual Interface.

Single ended termination of clock for dual link DVI receiver

The present invention comprises an apparatus and corresponding method for performing a built-in self-test (BIST) of a data communications system. The apparatus of the invention includes a transmitter, a receiver coupled to the transmitter and a test control system coupled to the transmitter and receiver for measuring a data error rate of the data communications system. The transmitter, receiver and test control system are disposed on a common substrate, such as an integrated circuit.

Apparatus and method for built-in self-test of a data communications system

High-performance, digital-to-analog conversion (DAC) suitable for use in systems implemented with low-voltage, low-power integrated circuit fabrication processes is disclosed. Encoder circuitry receives a binary number for which an analog representation is sought. Segments of the binary number are thermometer encoded and complemented to provide signals to drive analog conversion circuitry. The analog conversion circuitry includes sets of current cells, with each cell in a set contributing an equal amount to one or the other of the complementary legs of the analog output of the converter. Each current cell is a fully differential current switch with charge canceling, fed by a regulated cascode current source. The regulated cascode current source offers uncharacteristically high impedance that contributes to good circuit performance even in low-voltage, low-power implementations. Other design factors of the current cell contribute significantly to overall performance. Hierarchical gradient symmetry cancellation techniques are also employed to reduce integral non-linearity attributable to process-related surface gradients.

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Pasadena, CA, United States of America

David Vetea Greig