Formfactor, Inc.

Cubic Memory, Inc.

Other

Aeris Communications, Inc.

Vertical Circuits, Inc.

David V Pedersen

Igor Y Khandros

Benjamin N Eldridge

Gaetan L Mathieu

Kenneth M Sautter

Ralph G Whitten

Michael G Finley

Benjamin N Eldridge, Jr

Mohammad Eslamy

Harry D Cobb

Gary W Grube

Thomas H Dozier, Ii

Michael A Stadt

Douglas S Ondricek

Neil Pearson

Richard Stephen Roy

Dae Seong Kim

Syed Zaeem Hosain

Scott D Pedersen

Hein Dinh Ho

A damage prediction system that uses hazard data and/or aerial images to predict future damage and/or estimate existing damage to a structure is described herein. For example, the damage prediction system may use forecasted hazard data to predict future damage or use actual hazard data to estimate existing damage. The damage prediction system may obtain hazard data in which structures were or will be impacted by a hazard. The damage prediction system can then generate a flight plan that causes an aerial vehicle to fly over the impacted parcels and capture images. The damage prediction system can use artificial intelligence to process the images for the purpose of identifying potential damage. The damage prediction system can also use a hazard model, the hazard data, and structure characteristics to generate a damage score. The damage prediction system can then use the processed images and/or damage score to generate a virtual claim.

Damage prediction system using artificial intelligence

Embodiments of the invention provide methods and apparatuses for implementing telemetry applications with the SIM card of a mobile equipment. For one embodiment of the invention the telemetry application allows the encoding of TAD within a supplementary services message and transmission of the TAD over a control channel of a GMS telecommunications system. For one embodiment of the invention the telemetry application allows the decoding of caller identification message received from a CMS to obtain the TAD.

Methods and apparatus for implementing telemetry applications on a subscriber identity module

A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into contact with conductive terminals on devices under test.

Method of repairing segmented contactor

Microelectronic contact structures () are lithographically defined and fabricated by applying a masking layer () on a surface of a substrate () such as an electronic component, creating an opening () in the masking layer, depositing a conductive trace of a seed layer () onto the masking layer and into the openings, and building up a mass of conductive material on the conductive trace. The sidewalls of the opening can be sloped (tapered). The conductive trace can be patterned by depositing material through a stencil or shadow mask (). A protruding feature () may be disposed on the masking layer so that a tip end () of the contact structure acquires a topography. All of these elements can be constructed as a group to form a plurality of precisely positioned resilient contact structures.

Lithographically defined microelectronic contact structures

Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. A significant reduction in interconnect count and consequent simplification of the interconnection substrate is realized because the ASICs are capable of receiving a plurality of signals for testing the DUTs over relatively few signal lines from a host controller and promulgating these signals over the relatively many interconnections between the ASICs and the DUTs. The ASICs can also generate at least a portion of these signals in response to control signals from the host controller. Physical alignment techniques are also described. Micromachined indentations on the front surface of the ASICs ensure capturing free ends of the spring contact elements. Micromachined features on the back surface of the ASICs and the front surface of the interconnection substrate to which they are mounted facilitate precise alignment of a plurality of ASICs on the support substrate.

Wafer-level burn-in and test

Method of fabricating segmented contactor

Spring contact elements are fabricated by depositing at least one layer of metallic material into openings defined in masking layers deposited on a surface of a substrate which may be an electronic component such as an active semiconductor device. Each spring contact element has a base end, a contact end, and a central body portion. The contact end is offset in the z-axis (at a different height) and in at least one of the x and y directions from the base end. In this manner, a plurality of spring contact elements are fabricated in a prescribed spatial relationship with one another on the substrate. The spring contact elements make temporary (i.e., pressure) or permanent (e.g., joined by soldering or brazing or with a conductive adhesive) connections with terminals of another electronic component to effect electrical connections therebetween. In an exemplary application, the spring contact elements are disposed on a semiconductor devices resident on a semiconductor wafer so that temporary connections can be made with the semiconductor devices to burn-in and/or test the semiconductor devices.

Microelectronic spring contact elements

One embodiment of the present invention concerns a test assembly for testing product circuitry of a product die. In one embodiment, the test assembly includes at test die and an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die. The test die may be designed according to a design methodology that includes the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers. By partitioning the product circuitry and test circuitry into separate die, embedded test circuitry can be either eliminated or minimized on the product die. This will tend to decrease the size of the product die and decrease the cost of manufacturing the product die while maintaining a high degree of test coverage of the product circuits within the product die. The test die can be used to test multiple product die on one or more wafers.

Test assembly including a test die for testing a semiconductor product die

Products and assemblies are provided for socketably receiving elongate interconnection elements, such as spring contact elements, extending from electronic components, such as semiconductor devices. Socket substrates are provided with capture pads for receiving ends of elongate interconnection elements extending from electronic components. Various capture pad configurations are disclosed. Connections to external devices are provided via conductive traces adjacent the surface of the socket substrate. The socket substrate may be supported by a support substrate. In a particularly preferred embodiment the capture pads are formed directly on a primary substrate such as a printed circuit board.

Socket for making with electronic component, particularly semiconductor device with spring packaging, for fixturing, testing, burning-in or operating such a component

Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. Physical alignment techniques are also described.

Methods for processing at least one die which comprises an integrated circuit. In one example of a method of the invention, an identification code is applied to a carrier. A singulated die is deposited into the carrier which holds the singulated die. The singulated die comprises an integrated circuit. The identification code may be applied to the carrier before or after depositing the singulated die into the carrier. The carrier may be used in testing the singulated die and may include a plurality of singulated die or just one singulated die. In another example of a method of the invention, an identification code is applied to a die. The die is deposited into a carrier which holds the die. The die comprises an integrated circuit, and the carrier holds the die in singulated form. Typically the die is placed in the carrier without any packaging which may protect the die. The identification code may be applied to the die before or after it is deposited into the carrier.

Method for processing an integrated circuit

Segmented contactor

Socket for mating with electronic component, particularly semiconductor device with spring packaging, for fixturing, testing, burning-in or operating such a component

Growing community of inventors

Scotts Valley, CA, United States of America

David V Pedersen