Apple Inc.

Other

Cypress Semiconductor Corporation

Sony Electronics Inc

Sony Corporation

Hewlett-packard Company

Netlogic Microsystems, Inc

Sawyer Law Group, P.c.

Advanced Memory International, Inc.

Sony Corporation of Japan

Cypress Semiconductor Corportion

David V James

Jagadeesan Rajamanickam

Bruce Alan Fairman

Glen D Stone

Hisato Shima

Glen David Stone

Donald N North

Richard K Scheel

Scott D Smyers

Jose L Diaz

David S Hunter

Michael C Stephens, Jr

Brent Keeth

Peter B Gillingham

Cormac Michael O'Connell

Bruce Millar

Mario D Nemirovsky

Hans A Wiggers

Sanjay M Wanzakhade

David B Gustavson

Troy A Manning

Terry R Lee

Kevin J Ryan

William R Bryg

Yoshikazu Morooka

Michael D Teener

Steven T Mangelsdorf

Henry Stracovsky

William S Worley, Jr

Desi Rhoden

Terrence C Miller

Jung-Jen Liu

Michael J Mahon

Kevin M Christiansen

Bruce E Eckstein

William G Rivard

Steven C Boettner

Jagadecsan Raiamanickam

Kazonubu Toguchi

Hans Wiggors

Tso-Kai Liu

Jean Crepeau

A system and method for delaying packet transmissions within source devices and network bridges for the purpose of reducing the worst-case delays associated with forwarding of time-sensitive packets through a bridged network. The minimal bridged network system include a first device node attached to a first network link, a second device node attached to a second network link, and a bridge connecting the first network link to the second network link. The method and system includes shaping the traffic within a source device or bridge (shaping involves spreading bunched packets over time). Within a bridge, shaping occurs at each output port of the bridge, applying a distinct shaper to the traffic coming from each of the input ports, as well as distinct shapers for the distinct traffic class coming each of the input ports. According to the system and method disclosed herein, the present invention ensures small latencies when passing through network bridges, regardless of the network topology or other concurrent data-packet transfers, subject to the restriction that the cumulative time-sensitive bandwidth flowing through any link is less than the prenegotiated rate below that of the link's cumulative bandwidth capacity.

Method for pacing multi-rate time sensitive traffic on Ethernet and bridge connected networks

The present invention is a protocol for maintaining cache consistency between multiprocessors within a tightly coupled system. A distributed directory is maintained within the data-sharing processors, so that copies can be invalidated when modified. All transfers are event driven, rather the polled, to reduce bus-bandwidth consumption. Deadlocks are avoided by placing to-be-executed command codes in the returned response packets, when the request-forwarding queues are full or not present.

Method for maintaining cache coherence using a distributed directory with event driven updates

A method and apparatus for configuring signal lines with idle codes is disclosed. According to one embodiment, data transmission system () may include encoders (and) that transmit data over signal line lanes (Laneto Lane n). In an idle state, an encoder (and) may output one of at least two idle codes (IDLE A and IDLE B). One idle code (IDLE A) may indicate a first lane of a group of lanes. Another idle code (IDLE B) may indicate subsequent lanes of a group of lanes.

Method and apparatus for configuring signal lines according to idle codes

Method for pacing multi-rate time sensitive traffic on ethernet and bridge connected networks

A search engine system () is disclosed that can include at least one content addressable memory (CAM) device () arranged in a cascade configuration with at least one memory device (), such as a static random access memory (SRAM). A CAM device () and memory device () may be connected to one another by point-to-point unidirectional connections. Command data issued by a device, such as a network processing unit (NPU) (), can flow through all devices beginning with a CAM device () and eventually to a memory device (). A memory device () can compare its own current result data with that of a previous device in a flow (such as another RAM device), and generate an output response.

Random access memory (RAM) method of operation and device for search engine systems

According to one embodiment, a content addressable memory (CAM) device () may include a number of segments (or). Search target compare circuits (and) can compare a target value TARGET to programmable information values (PIVand PIV) associated with a particular segment (and). If a search target value TARGET matches a programmable information value (PIVand PIV), search operations may be performed in a segment (or). If a search target value TARGET does not match a programmable information value, (PIVand PIV), search operations may be prevented within a segment (or).

Content addressable memory (CAM) device having selectable access and method therefor

An asynchronous control mechanism packet is used to send control messages and information to one or more bridge devices within a network of buses of devices. The asynchronous control mechanism packet is addressed to a device on one of the buses and is intercepted by one or more appropriate bridge devices along the path to the destination device. The asynchronous control mechanism packet is targeted at a particular bridge device or used to send control messages and information to bridge devices along a particular communications route between two devices. The asynchronous control mechanism packet includes a designation specifying that it is an asynchronous control mechanism packet and should be treated accordingly. This designation is recognized by the appropriate bridge devices. Preferably, this designation is included within the extended transaction code field of the packet. In an alternate embodiment, the designation is included within a transaction code field of the packet. In a further alternate embodiment, the designation is included within an address offset value within the packet. Instructional information within the asynchronous control mechanism packet specifies to intercepting bridge devices the type of transaction and control tasks to be performed by the bridge device when the asynchronous control mechanism packet is received.

Method of and apparatus for implementing and sending an asynchronous control mechanism packet used to control bridge devices within a network of IEEE Std 1394 serial buses

According to a data packet framing method of one embodiment, a data packet () may include a combination control character () that may convey framing information FLAG (-) and a code information CODE (-). Framing information FLAG (-) can indicate a start of a packet, and a code information CODE (-) can indicate another feature of a packet, such as size. A combination control character () may preferably be no larger than a data character of a data packet.

Method and apparatus for framing a data packet

According to one embodiment, a content addressable memory (CAM) device () may include a number of CAM entry sets (-and-), each of which includes multiple CAM entries. CAM () may also include multiple programmable information registers (PIRs) (-and-), each of which can be associated with a CAM entry set (-and-). PIRs (-and-) may be accessed in response to CAM commands. Values stores in PIRs (-and-) may control access to associated CAM entry sets (-and-) and/or be output in response to predetermined operations in an associated CAM entry set (-and-).

Apparatus and method for associating information values with portions of a content addressable memory (CAM) device

According to an embodiment, a content addressable memory (CAM) device () may be capable of executing a 'restricted' search operation. A restricted search operation (an 'explore' or &#x201c;search beyond&#x201d; operation) may compare only a portion of the CAM entries to a search key device. Preferably, a restricted search operation may restrict searches to entries having an index value greater than a received search index value.

Method and apparatus for restricted search operation in content addressable memory (CAM) devices

A search engine system () and CAM device () are disclosed. A search engine system () may generate response packets () in response to requests packets () and include at least one content addressable memory (CAM) device (-) having an input interface (-) for receiving data packets and an output interface (-) for transmitting data packets.

Packet based communication for content addressable memory (CAM) devices and systems

A method and system thereof for organizing and accessing stored data in a mass storage unit such as a hard disk device. An object is associated with the stored data, and a unique object identifier is derived for and assigned to the object by the hard disk device. The object is addressed by its object identifier. The object is maintained in a hierarchical organization with other objects. The hierarchical organization includes an object list that contains the object identifier and also includes object identifiers for the other objects. Commands are defined for accessing and operating on the stored data using the object identifier for the object associated with the data. Thus, objects are named and organized on a hard disk device in an audio/visual network in a uniform manner, and the objects are represented to devices in the AV network so that they can be readily accessed and retrieved by those devices. In one embodiment, the unique object identifier includes a first portion representing a unique vendor number for the particular hard disk device and a second portion representing a unique assignment such as the date and time that the object was created.

AV/C commands for accessing a hard disk device

Growing community of inventors

Palo Alto, CA, United States of America

David V James