International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries Singapore Pte. Ltd.

Tokyo Electron Limited

Freescale Semiconductor,inc.

Semivation, LLC

Other

Samsung Electronics Co., Ltd.

Globalfoundries U.S. 2 LLC

International Business Machines Coirporation

David V Horak

Toshiharu Furukawa

Steven J Holmes

Mark Charles Hakey

Charles W Koburger, Iii

Shom Ponoth

Chih-Chao Yang

Peter H Mitchell

Jack Allan Mandelman

Larry Alan Nesbit

William H Ma

Takeshi Nogami

William R Tonti

Marc Adam Bergendahl

Chung H Lam

Su Chen Fan

Ruilong Xie

Elbert Emin Huang

Yunpeng Yin

Balasubramanian S Haran

Hemanth Jagannathan

Balasubramanian Pranatharthiharan

Sivananda K Kanakasabapathy

Wendell P Noble

Robert K Leidy

Ethan Harrison Cannon

Anthony K Stamper

Veeraraghavan S Basker

Daniel C Edelstein

Chun-chen Yeh

Satyanarayana Venkata Nitta

Gary Bela Bronner

Wesley Charles Natzle

Shyng-Tsong Chen

Chiahsun Tseng

James Gardner Ryan

Bruce Bennett Doris

Edward J Nowak

Robert J Gauthier, Jr

Steven H Voldman

Sanjay C Mehta

Edmund Juris Sprogis

Merritt Funk

Terry Allen Spooner

Howard L Kalter

Gerhard Ingmar Meijer

Robert Michael Geffken

Theodorus E Standaert

Jed Hickory Rankin

Xiuyu Cai

Wai-Kin Li

Muthumanickam Sankarapandian

Sean David Burns

James Stuart Dunn

John Christopher Arnold

Hon-Sum Philip Wong

James Marc Leas

Douglas C La Tulipe, Jr

Kangguo Cheng

Ali Khakifirooz

Brent A Anderson

Effendi Leobandung

Junli Wang

Carl John Radens

Son Van Nguyen

Christopher J Penny

Baozhen Li

Lee Chen

Hosadurga K Shobha

Robert H Dennard

James Albert Slinkman

Randy William Mann

Eric J Strang

Jeffrey Scott Brown

Thomas L McDevitt

Ulrike Gruening

Charles Thomas Black

Stanislav Polonsky

Leathen Shi

Samuel S Choi

Harold G Linde

Ying Di Zhang

Kirk David Peterson

Stephen McConnell Gates

Matthew Earl Colburn

Richard Stephan Wise

Dirk Pfeiffer

Omer H Dokumaci

Qiqing Christine Ouyang

Dario Leonardo Goldfarb

Rajarao Jammy

David Lee Rath

James Spiros Nakos

Gregory Breyta

David M Dobuzinsky

Nicholas C M Fuller

Katherina E Babich

Scott David Halle

Maheswaran Surendra

Michael D Armacost

A method of fabricating a single-crystal silicon photovoltaic cell includes providing a single-crystal silicon wafer and a structural support member. The single-crystal silicon wafer has a first major surface and a second major surface. Each major surface extends along a major surface plane. The single-crystal silicon wafer has a thickness greater than 100 micrometers and a dimension greater than 50 mm. The method further includes mounting the structural support member to the first major surface or to the second major surface. The method further includes reducing thickness of the single-crystal silicon wafer to a thickness less than or equal to 100 micrometers while the single-crystal silicon wafer is mounted to the structural support member. The method further includes providing the first major surface with a diffusion and a metalization grid and providing the second major surface with a back surface contact.

Thin single-crystal silicon solar cells mounted to a structural support member and method of fabricating

A method of cleaving off a daughter single crystal substrate from a parent single crystal substrate includes providing a stress-mandrel and the parent a single crystal substrate. The parent single crystal substrate has a major surface and an edge surface that intersects the major surface. The major surface extends along a major surface plane. The stress-mandrel has a stress-mandrel coefficient of thermal expansion that is higher than the parent single crystal coefficient of thermal expansion. The method includes bonding the stress-mandrel to the major surface, and cooling the parent single crystal substrate and the stress-mandrel. The cooling of the parent single crystal substrate bonded to the stress-mandrel provides a thermal stress in the parent single crystal substrate sufficient to cleave the parent single crystal substrate. The cleaving extends substantially along a plane parallel to the plane of the major surface. In one embodiment the cleaved daughter substrate was used to make a photovoltaic cell.

Method of cleaving a single crystal substrate parallel to its active planar surface and method of using the cleaved daughter substrate

A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.

Size-filtered multimetal structures

A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions.

Non-lithographic line pattern formation

A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.

Gate contact with vertical isolation from source-drain

A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions. A planarization dielectric layer is formed over the raised active semiconductor regions. In one embodiment, the dielectric disposable gate structure is removed, and a dielectric gate spacer can be formed by conversion of surface portions of the raised active semiconductor regions around a gate cavity. Alternately, an etch mask layer overlying peripheral portions of the disposable gate structure can be formed, and a gate cavity and a dielectric spacer can be formed by anisotropically etching an unmasked portion of the dielectric disposable gate structure. A replacement gate structure can be formed in the gate cavity.

Replacement gate electrode with a self-aligned dielectric spacer

Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

Self-aligned dielectric isolation for FinFET devices

A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material.

Borderless contact structure

A semiconductor structure which includes: a fin on a semiconductor substrate; and a gate structure wrapped around the fin. The gate structure includes: spaced apart spacers to form an opening, the spacers being perpendicular to the fin, the spacers having a height with respect to the fin; a high-k dielectric material in the opening and over the fin, the high-k dielectric material in contact with the spacers and a bottom of the opening; a work function metal in contact with the high-k dielectric material that is over the fin, the spacers and the bottom of the opening, the work function metal that is in contact with the high-k dielectric material having a height in the opening that is less than the height of the spacers, the high-k dielectric material and the work function metal only partially filling the opening; and a metal completely filling the opening.

Replacement metal gate

An integrated circuit structure with a selectively formed and at least partially oxidized metal cap over a gate. In one embodiment, an integrated circuit structure has: a substrate; a metal gate located over the substrate; at least one liner layer over the substrate and substantially surrounding the metal gate; and an at least partially oxidized etch stop layer located directly over the metal gate, the etch stop layer including at least one of cobalt (Co), manganese (Mn), tungsten (W), iridium (Ir), rhodium (Rh) or ruthenium (Ru).

Integrated circuit structure having selectively formed metal cap

A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer.

Dual hard mask lithography process

A method is provided for fabricating an integrated circuit that includes multiple transistors. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap.

Silicon-on-insulator transistor with self-aligned borderless source/drain contacts

Growing community of inventors

Albany, NY, United States of America

David V Horak