Stmicroelectronics S.a.

David Turgis

Jean-Christophe Lafont

Olivier Menut

Bertrand Borot

Christophe Frey

Anis Feki

Lorenzo Ciampolini

Electronic component including a ternary content-addressable memory component, configured to compare the input data items with a set of pre-recorded reference data words; the memory component incorporates a matrix of elementary cells arranged in lines and columns; each line incorporates cells in each of which is recorded one bit of one of the reference data words; the cells of a given column are dedicated to the comparison of the same bit of the input data word; each cell incorporates: two memory points storing the data representing the reference data bit; a comparison circuit connected to the memory points, with a comparison point of which the potential represents the comparison if the input data bit and the data stored in the memory points, and also incorporating a common comparison circuit to which are connected the comparison circuits of all or part of the cells of a given column; the comparison circuit incorporates terminals to which the bit from the input data word and its complement are applied.

Electronic component including a matrix of TCAM cells

A volatile memory including volatile memory cells adapted to the performing of data write and read operations. The memory cells are arranged in rows and in columns and, further, are distributed in separate groups of memory cells for each row. The memory includes a first memory cell selection circuit configured to perform write operations and a second memory cell selection circuit, different from the first circuit, configured to perform read operations. The first circuit is capable of selecting, for each row, memory cells from one of the group of memory cells for a write operation. The second circuit is capable of selecting, for each row, memory cells from one of the groups of memory cells for a read operation.

Volatile memory with a decreased consumption

A measuring circuit is provided for a memory integrated within a semiconductor device. The measuring circuit includes initializing means and an oscillating loop. The initializing means loadings two complementary values into at least two locations of the memory. The two locations are addressed by a first address and a second address. The oscillating loop comprises a logic circuit for alternatively generating the first address and the second address from data read from the memory so as to successively read data from the first and second memory locations to produce an oscillating signal that has a frequency that depends on internal parameters of the memory. Also provided is a method for qualifying a memory by initializing the memory by loading two complementary values into two locations, and generating an oscillating signal with a frequency that is dependent on internal parameters of the memory.

Measuring circuit for qualifying a memory located on a semiconductor device

A memory cell (), includes a flip-flop () that has additional read/write terminals; a 1-bit write line (wb); a first transistor (T) switching between the 1-bit write line and the terminal, its gate being connected to a word selection line (W); a 0-bit write line (wb); a second transistor (T) switching between the 0-bit write line and the terminal, its gate being connected to a word selection line (W); a bit read line (b); and read transistors (T, T), with one of their gates being connected to a read/write terminal and the other being connected to a word selection line.

Random access memory cell of reduced size and complexity

A ROM-type memory is provided that includes a matrix of memory cells made up of rows and columns, with each row allowing storage of a page of MUX words of N bits. An address decoder decodes addresses in order to extract the page to be read. At the output of the matrix, N multiplexers are each coupled to the columns that correspond to one of the bits of the output stage. An N-bit output stage includes at least one inverter, with each of the inverters being connected to the output of one of the multiplexers so as to restore inverted values of information to be stored to correct values. The inverted values are stored in all of the memory cells of all of the columns coupled to the one multiplexer. Storing the inverted values makes it possible to store less '0' values within the matrix and further makes LVS testing of the ROM memory considerably easier. Also provided is a method for sequentially checking groups of memory cells.

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Le Touvet, France

David Turgis