Allegro Microsystems, LLC

Transwitch Corporation

Other

David Toebes

Subhash Chandra Roy

Michael M Renault

Frederick R Carter

Rajen S Ramchandani

William P Taylor

Gregory Szczeszynski

Michael C Doogue

Alexander Latham

Bryan Cadugan

Daniel C Upp

Craig S Petrie

Igor Zhovnirovsky

Pranav Raval

Steven Benoit

Naota Nakayama

Benjamin Geiger

A method of detecting a vibration comprises determining a vibration flag has been set during a running mode of the magnetic field sensor, remaining in the running mode until a predetermined number of vibration flags have been set, and entering a recalibration mode when the predetermined number of vibration flags have been set. A counter can be implemented for each of the plurality of vibration flags to determine if the predetermined number of vibration flags have been set.

System and method for vibration detection with direction change response immunity using a magnetic field sensor

A system includes a magnetic target and a magnetic field sensor. The magnetic field sensor comprises an output node; a circuit to detect a magnetic field produced by the magnetic target; and a processor. The processor may be configured to transmit a signal onto the output node representing the detected magnetic field; detect whether the transmitted signal is interrupted by an external source; and, if the signal is interrupted, initiate a self-test of the apparatus. Corresponding methods and apparatuses are also disclosed.

Magnetic field sensors with self test

An electronic circuit for driving a plurality of light emitting diode (LED) channels coupled to a common voltage node includes a priority queue for tracking a dominant LED channel. A queue manager may be provided to keep the priority queue updated during LED drive operations based on operating conditions associated with the LED channels.

LED driver having priority queue to track dominant LED channel

Methods and apparatus for providing a position sensor to sense the position of a ferromagnetic target and generate a target position signal, a scaling block to receive the target position signal, and a digital RC filter to generate an output using bit shifting for dividing by some factor of two, wherein all division for computations in the RC filter are performed by bit shifts.

Methods and apparatus for positioning a coil motor

Methods and apparatus for phase and frequency drift and jitter compensation in a distributed switch which carries both TDM and packet data are disclosed. The methods include the insertion of programmable fill times at different stages of the switch to allow buffers to fill, driving service processors (line cards) with different clocks and synchronizing the service processors (line cards) to the switch fabric, providing redundant switch fabric clocks and methods for automatically substituting one of the redundant clocks for a clock which fails, providing redundant switch fabrics each having a different clock and methods for automatically substituting one switch fabric for the other when one fails. The apparatus of the invention includes a plurality of service processors (line cards), switch elements and clock generators. An exemplary clock generator based on an FPGA is also disclosed.

Phase and frequency drift and jitter compensation in a distributed telecommunications switch

A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the port processor has a total I/O bandwidth equivalent to an OC-48, and the switch element has 12&#xd7;12 ports for a total bandwidth of 30 Gbps. A typical switch includes multiple port processors and switch elements. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data from a port processor through one or more switch elements to the same or another port processor. Each frame is transmitted in 125 microseconds; each row in 13.89 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The slot bandwidth is 2.592 Mbps which is large enough to carry an E-1 signal with overhead. The 4-bit tag is a cross connect pointer which is setup when a TDM connection is provisioned. The last twenty slots of the frame are reserved for link overhead. Thus, the frame is capable of carrying the equivalent of 1,680 E-1 TDM signals. For ATM and packet data, a PDU (protocol data unit) of 16 slots is defined for a 64-byte payload. The PDUs are self-routed through the switch with a 28-bit routing tag which allows routing through seven switch stages using 4-bits per stage. Bandwidth is arbitrated among ATM and Packet connections while maintaining TDM timing.

Method and apparatus for arbitrating bandwidth in a communications switch

A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the port processor has a total I/O bandwidth equivalent to an OC-48, and the switch element has 12&times;12 ports for a total bandwidth of 30 Gbps. A typical switch includes multiple port processors and switch elements. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data from a port processor through one or more switch elements to the same or another port processor. Each frame is transmitted in 125 microseconds; each row in 13.89 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The slot bandwidth is 2.592 Mbps which is large enough to carry an E-1 signal with overhead. The 4-bit tag is a cross connect pointer which is setup when a TDM connection is provisioned. The last twenty slots of the frame are reserved for link overhead. Thus, the frame is capable of carrying the equivalent of 1,680 E-1 TDM signals. For ATM and packet data, a PDU (protocol data unit) of 16 slots is defined for a 64-byte payload. The PDUs are self-routed through the switch with a 28-bit routing tag which allows routing through seven switch stages using 4-bits per stage. Bandwidth is arbitrated among ATM and Packet connections while maintaining TDM timing.

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Andover, MA, United States of America

David Toebes