Synopsys, Inc.

David Thomas Reid

Plamen A Asenov

Salvatore Maria Amoroso

Manuel Aldegunde Rodriguez

Binjie Cheng

Andrew John Pender

Jaehyun Lee

Andrew R Brown

The design of Dynamic Random Access Memory (DRAM) pass transistors is provided via generating a first plurality of transistor leakage currents by simulating different dopant configurations in a transistor; generating a second plurality of transistor leakage currents by simulating, for each dopant configuration of the different dopant configurations, a single trap insertion in the transistor; fitting the first and second pluralities of transistor leakage currents with first and second leakage current distributions; combining the first and second leakage current distributions to produce a third leakage current distribution; generating a third plurality of statistically generated leakage currents for a specified trap density for the transistor based on the first leakage current distribution, on the second leakage current distribution and on a specified trap density; and modeling and evaluating a DRAM cell including the transistor based on the third plurality of statistically generated leakage currents.

Dynamic random-access memory pass transistors with statistical variations in leakage currents

A method for generating semiconductor device model parameters includes receiving semiconductor device performance data of statistical instances of semiconductor devices, for a plurality of coordinates in a process space with dimensions of process-dependent device parameters Model parameters are extracted to produce individual model instances, each corresponding to the respective statistical instances for the coordinates in the process space. Statistics of the extracted model parameters are modeled by processing the individual model instances to determine, for each coordinate in the process space, moments describing non-normal marginal distributions of the extracted model parameters and correlations between the extracted model parameters. Semiconductor device model parameters are generated for use in simulating a circuit using the determined moments and the determined correlations, for a selected coordinate in the process space.

Parameter generation for modeling of process-induced semiconductor device variation

A method for generating semiconductor device model parameters includes receiving semiconductor device performance data of statistical instances of semiconductor devices, for a plurality of areal trapped charge densities Model parameters are extracted to produce individual model instances, each corresponding to the respective statistical instances for the areal trapped charge densities. Statistics of the extracted model parameters are modeled by processing the individual model instances to determine, for each areal trapped charge density, moments describing non-normal marginal distributions of the extracted model parameters and correlations between the extracted model parameters. Semiconductor device model parameters are generated for use in simulating a circuit using the determined moments and the determined correlations, for a selected areal trapped charge density.

Parameter generation for semiconductor device trapped-charge modeling

Growing community of inventors

Glasgow, United Kingdom

David Thomas Reid