Fujitsu Corporation

David Thach

Ryosuke Oishi

Yutaka Tamiya

Atsushi Ike

Hirotaka Tamura

Sanroku Tsukamoto

Hisanori Fujisawa

Arithmetic circuits calculate d&#x2212;1 energy values (hto h) indicating energies generated by 2-body to d-body coupling on the basis of a plurality of weight values indicating strength of 2-body to d-body coupling of 2 to d neurons including a first neuron whose output value is allowed to be updated and n-bit output values of n neurons. An adder circuit calculates a sum of these values, and a comparator circuit compares a value based on a sum of the sum and a noise value with a threshold, to determine the output value of the first neuron. An update circuit outputs n-bit updated output values in which one bit has been updated on the basis of a selection signal and the output value of the first neuron. The holding circuit holds the updated output values and outputs the updated output values as the n-bit output values used by the arithmetic circuits.

Information processing apparatus, ising device, and information processing apparatus control method

A simulation apparatus includes a memory, and a second processor configured to detect an internal state of the first processor in the operation simulation, when a target block in the operation simulation changes, the target block being included in blocks obtained by dividing code of the program, generate association information in which the internal state detected by the detecting section and performance values of instructions included in the target block in the detected internal state are associated with each other, and execute an execution code that allows a performance value when the first processor executes the target block to be calculated based on the association information, by using the internal state detected and the association information generated for the target block, to thereby calculate a performance value when the first processor executes the target block.

Simulation apparatus and storage medium

An information processing apparatus has a processor and a programmable logic circuit device (PLD) that includes a reconfiguration region to configure a logic circuit requested by a configuration request from the processor. The processor compares a first execution time of a plurality of the logic circuits for a case when a degree of parallelism adjustment is performed by decreasing a degree of parallelism of a first logic circuit and increasing a degree of parallelism of a second logic circuit and a second execution time of the plurality of logic circuits for a case when the degree of parallelism adjustment is not performed, and requests the degree of parallelism adjustment to the PLD when the first execution time is shorter than the second execution time, and does not request the degree of parallelism adjustment to the PLD when the first execution time is not shorter than the second execution time.

Information processing apparatus, PLD management program and PLD management method

A communication apparatus internally generates a virtual terminal (emulator) of a mobile terminal. The virtual terminal performs handover to a 3G network in place of the mobile terminal. In the event of an incoming call to the mobile terminal, the virtual terminal receives the call in place of the mobile terminal and notifies the mobile terminal of the call. Consequently, without having to perform handover, the mobile terminal is able to receive communication notification, whereby telephone communication by the mobile terminal remains enabled without the expenditure of power for handover, enabling a reduction in power consumption.

Communication system, communication program, communication apparatus, mobile terminal and, communication method

A code converterof a simulation apparatusdetects, during the execution of a program in a target CPU, an externally dependent instruction affected by the external environment in each of divided blocks, predicts the execution result of the externally dependent instruction, simulates the instruction execution in the predicted result, and generates a host code in which a code for performance simulation is embedded based on the simulation result. A simulation executorperforms performance simulation about instruction execution in the prediction result of the program using the host code, and when the execution result of the externally dependent instruction is different from the setting of the prediction result during the execution, corrects the execution time of the instruction in the prediction result using the execution time of instructions executed before and after the instruction, and the like. A simulation information collectorcollects and outputs performance simulation information.

Simulation apparatus, method and medium

A communication device includes a memory and a processor coupled to the memory. The processor executes a process including calculating an amount of electricity available in a second device while a first communication unit and a second communication unit with each other, determining a first generation unit to be a generation unit, when the amount of electricity thus calculated is smaller than a predetermined amount, out of the first generation unit that generates navigation information based on information acquired by an information acquisition unit and a second generation unit, and controlling the second device so as to stop supplying power to the second generation unit and to output the navigation information generated by the first generation unit when the first generation unit is determined.

Communication device, mobile terminal, medium, information generation method, and system

A non-transitory, computer-readable recording medium stores therein a verification support program that causes a computer to execute identifying from a finite state machine model related to a circuit-under-test, an input count of transitions to a transition-end state and an output count of transitions from the transition-end state; determining the transition-end state to be a record/restore subject, if the identified output transition&#x3e;the identified input transition count; embedding record-instruction information causing the record/restore subject to be recorded to a database, if a first element causing transition to the record/restore subject is included in a first test scenario that is in a test scenario group related to the circuit-under-test; and embedding restore-instruction information causing the record-restore subject to be restored from the database, if a second element causing transition to the record-restore subject is included in a series of elements making up a second test scenario that is in the test scenario group.

Verification support computer product, apparatus, and method

A verification support program that causes a computer to execute identifying from a finite state machine model related to a circuit-under-test, an input count of transitions to a transition-end state and an output count of transitions from the transition-end state; determining the transition-end state to be a record/restore subject, if the identified output transition is greater than the identified input transition count; embedding record-instruction information causing the record/restore subject to be recorded to a database, if a first element causing transition to the record/restore subject is included in a first test scenario that is in a test scenario group related to the circuit-under-test; and embedding restore-instruction information causing the record-restore subject to be restored from the database, if a second element causing transition to the record-restore subject is included in a series of elements making up a second test scenario that is in the test scenario group.

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Kawasaki, Japan

David Thach