Microsoft Technology Licensing, LLC

University of Notre Dame Du Lac

Cray Incorporated

David Tennyson Harper, Iii

Eric Clarence Peterson

Christian L Belady

Shaun L Harris

Gagan Gupta

Douglas Christopher Burger

Rodney Wayne Smith

Thomas Philip Speier

Michael Scott McIlvaine

David A Maltz

Charles David Callahan, Ii

Darko Kirovski

Ming Zhang

Burton Jordan Smith

Brian Stempel

Gregory Joseph McKnight

Antony Ian Taylor Rowstron

Austin N Donnelly

Yusuf Cagatay Tekmen

Parag Sharma

Stephen Francis Heil

Adam B Glass

Robert Douglas Clancy

Peter M Kogge

Melinda Joyce Brown

Sergey Legtchenko

Ripal Babubhai Nathuji

David Alex Butler

Ji Yong Shin

Christopher Hanaoka

Shobana M Balakrsihnan

Jay B Brockman

A method described herein includes an act of receiving data that is indicative of predicted weather conditions for a particular geographic region, wherein the particular geographic region has an energy generation system therein, and wherein the energy generation system utilizes at least one renewable energy resource to generate electrical power. The method also includes the act of scheduling a computational workload for at least one computer in a data center based at least in part upon the data that is indicative of the predicted weather conditions for the particular geographic region.

Managing computational workloads of computing apparatuses powered by renewable resources

Exemplary reach-based explicit dataflow processors and related computer-readable media and methods. The reach-based explicit dataflow processors are configured to support execution of producer instructions encoded with explicit naming of consumer instructions intended to consume the values produced by the producer instructions. The reach-based explicit dataflow processors are configured to make available produced values as inputs to explicitly named consumer instructions as a result of processing producer instructions. The reach-based explicit dataflow processors support execution of a producer instruction that explicitly names a consumer instruction based on using the producer instruction as a relative reference point from the producer instruction. This reach-based explicit naming architecture does not require instructions to be grouped in instruction blocks to support a fixed block reference point for explicit naming of consumer instructions, and thus is not limited to explicit naming of consumer instructions only within the same instruction block of the producer instruction.

Reach-based explicit dataflow processors, and related computer-readable media and methods

Techniques described herein are directed to ensuring register data consistency between different instruction blocks. For example, a block-based processor renames registers during block decode, but delays the update of a logical register-to-physical register mapping utilized by other instruction blocks until it is determined that a write instruction configured to write to a logical register commits. Alternatively, the processor renames registers during block decode and updates the mapping accordingly. However, the update is negated (e.g., rolled back) if the write instruction is not executed. Still further, the processor may analyze the instructions in the block to determine instructions configured to write to a logical register but that will not execute due to a mismatched predicate. Based on the determination, the block-based processor ensures data consistency by copying data from a previously-assigned register to a newly-assigned register. Techniques may also be utilized to assist the block-based processor in determining such instructions.

Register renaming-based techniques for block-based processors

Operand-based reach explicit dataflow processors, and related methods and computer-readable media are disclosed. The operand-based reach explicit dataflow processors support execution of a producer instruction that explicitly names a target consumer operand of a consumer instruction in a consumer operand encoding namespace of the producer instruction. The produced value from execution of the producer instruction is provided or otherwise made available as an input to the named target consumer operand of the consumer instruction as a result of processing the producer instruction. The target consumer operand is encoded in the producer instruction as an operand target distance relative to the producer instruction. Instructions in an instruction stream between the producer instruction and the targeted consumer instruction that have no operands do not consume an operand reach namespace in the producer instructions. This provides for a deeper explicit consumer naming reach for a given bit size of the operand reach namespace.

Operand-based reach explicit dataflow processors, and related methods and computer-readable media

The transmission of multiple copies of data to other computing devices is optimized by minimizing the number of copies of such data transmitted through an expensive portion of the network. A store-and-forward methodology is utilized to transmit only a single copy through the expensive portion and the data is subsequently forked into multiple copies directed to multiple destination computing devices. Computing devices that are not intended destinations can be conscripted as intermediate computing devices, if appropriate to minimize copies of the data transmitted through an expensive portion. Additionally, accommodation can be made for data that is intolerant of out-of-order delivery by utilizing adaptive protocols that avoid mechanisms that may result in out-of-order delivery for data intolerant of such and by utilizing packet sorting at data convergence points to reorder the data. Different protocol settings can be utilized to transmit data across different portions of the network.

Network routing modifications for distribution of data

A data center includes a plurality of computing units that communicate with each other using wireless communication, such as high frequency RF wireless communication. The data center may organize the computing units into groups (e.g., racks). In one implementation, each group may form a three-dimensional structure, such as a column having a free-space region for accommodating intra-group communication among computing units. The data center can include a number of features to facilitate communication, including dual-use memory for handling computing and buffering tasks, failsafe routing mechanisms, provisions to address permanent interface and hidden terminal scenarios, etc.

Data center using wireless communication

A system is described herein that includes a predictor component that predicts accesses to portions of asymmetric memory pools in a computing system by a virtual machine, wherein the asymmetric memory pools comprise a first memory and a second memory, and wherein performance characteristics of the first memory are non-identical to performance of the second memory. The system also includes a memory management system that allocates portions of the first memory to the virtual machine based at least in part upon the accesses to the asymmetric memory pools predicted by the predictor component.

Virtual machine memory management in systems with asymmetric memory

A bid-based network sells network capacity on a transaction-by-transaction basis in accordance with bids placed on transactions. A transaction is the transmission of a quantum of data across at least some portion of the network, where the quantum of data can be as small as a single packet. Bids for network capacity are ranked in order of monetary value, or other criteria relevant to the network service provider. The amount charged to the highest bidder is based on the maximum bid of the next highest bidder. Bids are evaluated on a real-time basis at the time when the link is ready to transmit data. An automated system makes individual bids at each link through which data is transmitted and can take into account additional criteria that can be specified as part of the bid information, including latency and routing requirements. Bid information is passed with data through the network.

Incremental valuation based network capacity allocation

A method to exchange data in a shared memory system includes the use of a buffer in communication with a producer processor and a consumer processor. The cache data is temporarily stored in the buffer. The method includes for the consumer and the producer to indicate intent to acquire ownership of the buffer. In response to the indication of intent, the producer, consumer, buffer are prepared for the access. If the consumer intends to acquire the buffer, the producer places the cache data into the buffer. If the producer intends to acquire the buffer, the consumer removes the cache data from the buffer. The access to the buffer, however, is delayed until the producer, consumer, and the buffer are prepared.

Management of ownership control and data movement in shared-memory systems

Low cost storage for write once read rarely data is described. In an embodiment a storage device comprises a plurality of hard disk drives connected to a server via an interconnect fabric. The storage device comprises a cooling system which is only capable of cooling a first subset of the hard disk drives and a power supply system which is only capable of powering a second subset of the hard disk drives and in some examples, the interconnect fabric may be only capable of providing full bandwidth for a third subset of the hard disk drives. Each subset may comprise only a small fraction of hard disk drives. A control mechanism, which may be implemented in software, is provided which controls which hard disk drives are active at any time in order that the constraints set by the cooling and power supply systems and interconnect fabric are not violated.

Low cost storage for rarely read data

The claimed matter provides systems and/or methods that effectuate utilization of fine-grained concurrency in parallel processing and efficient management of established memory structures. The system can include devices that establish memory structures associated with individual processors that can comprise a parallel processing phalanx. The system can thereafter utilize various enqueuing and/or dequeuing directives to add or remove work descriptors to or from the memory structures individually associated with each of the individual processors thereby providing improved work flow synchronization amongst the processors that comprise the parallel processing complex.

Hardware support for work queue management

Embodiments of the present invention provide a class of computer architectures generally referred to as lightweight multi-threaded architectures (LIMA). Other embodiments may be described and claimed.

Growing community of inventors

Seattle, WA, United States of America

David Tennyson Harper, Iii