Xilinx, Inc.

Agilent Technologies, Inc.

Limpet Holdings (uk) Limited

The University of Liverpool

Edinburgh University

David Taylor

Matthew H Klein

Vincent Vendramini

Stuart Armstrong

Mark Blaxter

Alex Ballantyne

Ben Makepeace

Paolo Novellini

Douglas Michael Grant

Gareth David Edwards

Stuart Alan Nisbet

David Alexander Bisset

Simon Babayan

Simon Babayon

Duncan Andrew Cockburn

Alastair J Richardson

The present invention relates to vaccines comprising a ShK domain of a filarial nematode protein. These vaccines may be used for the prevention and/or treatment of filarial nematode infections. The invention also relates to novel proteins comprising a ShK domain of a filarial nematode protein and pharmaceutical compositions. The invention may be used for the prevention and/or treatment of filarial nematode infections in canine subjects, and also in human subjects.

Filarial nematode vaccines, polypeptides, and nucleic acids

A device includes a physical medium attachment (PMA), a physical coding sublayer (PCS), a phase detector, and an oscillator. The PMA receives data at a first speed and overclocks the received data to a second speed, wherein the second speed is higher than the first speed. The PCS receives the data at the second speed. The phase detector receives another data from the PCS wherein the another data is based on the received data at the second speed or the phase detector is configured to receive the data at the second speed directly from the PMA. The phase detector adjusts a phase based on bit transitions. The oscillator is coupled to the phase detector and generates a reference clock signal wherein a phase of the reference clock is adjusted by the phase detector. The oscillator clocks the PMA based on the adjusted clock.

Low latency receiver

The present invention relates to an apparatus for transferring an object from or to a marine transport vessel to or from a construction or vessel. The apparatus comprises a motive force generator; a motive force applicator operably linked to the motive force generator; and, in use of the apparatus, adapted to be operably linked to an object to which the motive force applicator applies a motive force; a fastening device for operably linking the motive force applicator to the object; a control mechanism; said control mechanism being formed and arranged so as to control the motive force generator and is operable to switch the operation of the motive force generator into an ascent or descent mode wherein the motive force generator acts upon the motive force applicator; and a measuring device operably linked to the control mechanism, said measuring device comprising one or more sensors and adapted to determine a distance between said measuring device and at least one point of a surface of a marine transport vessel from or to which said object is to be transferred wherein said apparatus further comprises one or more safety protocols and a parameter sensing means, said control mechanism being in communication with said parameter sensing means and responsive to feedback from said parameter sensing means, and adapted to initiate said one or more safety protocols.

Apparatus for and method of transferring an object between a marine transport vessel and a construction or vessel

An example pulse generation circuit includes a parallel-to-serial circuit configured to convert parallel data to serial data according to parallel clock signal and a serial clock signal, the serial data comprises a sequence of pulses; a clock generator configured to generate a clock signal; and a phase controller configured to generate the serial clock signal from the clock signal based on a phase control signal.

Precision pulse generation using a serial transceiver

In a method for buffering, a buffer buffers data responsive to read and write clock signals. A flag signal from the buffer is for a fill level thereof. The flag signal is toggled responsive to the data buffered being either above or below a set point for the fill level. A phase of the write clock signal is adjusted to a phase of the read clock signal responsive to the toggling of the flag signal. The write clock signal is used to control latency of the buffer. The adjusting of the phase of the write clock signal includes: generating an override signal responsive to the toggling of the flag signal; and inputting the read clock signal and the override signal to a phase adjuster to controllably adjust the phase of the write clock signal to the phase of the read clock signal during operation.

Latency control in a transmitter/receiver buffer

An embodiment of an apparatus includes a detector to receive a first input signal and a second input signal to provide a first error signal and a second error signal. A pulse width determination block receives the first and second error signals, as well as a digital oscillating signal, to output a first pulse width value and a second pulse width value, respectively. A pulse width accumulator accumulates the first and second pulse width values responsive to at least one cycle of the digital oscillating signal to provide a first accumulated value and a second accumulated value. An error generator provides an error value as a difference between the first accumulated value and the second accumulated value. The error value represents a pulse width difference between the first input signal and the second input signal indicative of a phase difference between the first input signal and the second input signal.

Pulse width determination for phase detection

A circuit generates an output clock signal synchronized to an input clock signal. The circuit includes a reference clock port, a phase interpolator, and a phase controller. The reference clock port receives a reference clock signal. The phase interpolator generates the output clock signal that, as a function of a variable control value, is an interpolation between two reference phases. The reference phases are generated from the reference clock signal and have a reference frequency. The phase controller generates the variable control value providing a phase rotation rate. An output frequency of the output clock signal equals a sum of the reference frequency and the phase rotation rate. The output frequency matches an input frequency of the input clock signal.

Circuit for generating an output clock signal synchronized to an input clock signal

A belay device for protecting a climber on a rope from a fall has a powered winding reel to which the rope is attached. A control mechanism acts to prevent slack in the rope between the climber and the winding reel and includes load sensor that which, on detecting the weight of the climber on the rope, switches the operation of the device to a fall or descent mode where the winding reel is stopped and the climber is suspended by the rope. An electronic control and diagnostic system monitors the operation of the winding reel and switches its operation to a safe, fault mode when a fault is detected.

Belay device

Measuring transit time across an asynchronous first-in-first-out (FIFO) memory can include sampling an indication of a value of a read pointer of the FIFO memory at a sampling frequency that exceeds a frequency of a read clock and a write clock of the FIFO memory. An indication of a value of a write pointer of the FIFO memory can be sampled at the sampling frequency. For each sampling period, a measure of occupancy of the FIFO memory can be calculated according to a sampled pair including the indication of the value of the read pointer and the indication of the value of the write pointer. The measure of occupancy can be averaged over a predetermined number of cycles of the sampling frequency. The averaged measure of occupancy can be output as an indication of transit time across the FIFO memory.

Determining transit time across an asynchronous FIFO memory by measuring fractional occupancy

The apparatus measures timing variations, such as the jitter or wander in a timing signal () of a telecommunications network. A recovered clock signal is sampled and digitized to produce a series of digital clock samples which are then processed () with reference to a local digital reference signal to produce digital baseband frequency in-phase (I) and quadrature (Q) components () these being further processed () to produce the digital phase information of said clock signal to determine () the required parameters of the network. The step of digitally processing said clock samples with reference to a local reference signal can be conveniently and cheaply implemented using a digital signal down-converter IC (), for example of a type existing for digital radio receiver implementations. For jitter measurement, the local reference signal may be generated by a phase-locked loop (as in FIG.). For wander measurements an external reference clock is used (as in FIG.).

Network measurement method and apparatus

An electronic system parameter, such as time deviation (TDEV), is measured by reference to an input series of data samples received and processed to produce in real-time first and second time-varying series of measurements for the parameter.

Method and apparatus for measuring parameters of an electrical system

Timing errors in digital transmission systems, such as maximum time interval error, are measured with data samples processed in a first stage to produce in real-time a first, time-varying series of measurements for a given parameter over observation intervals of a first magnitude. Each observation interval is many times longer than the sample period of the input series. Subsequent stages derive further measurements, corresponding to increasingly longer observation intervals, derived by treating previous observation intervals as sub-intervals. The first stage derives intermediate results for a predetermined interval and repeats for successive sub-intervals. The intermediate results are stored in a first first-in, first-out (FIFO) data set and updated at least once per sub-interval and the required parameter is derived. The second and subsequent stages similarly derive the required parameter corresponding to increasing observation interval magnitudes and update the measurements as data sets update.

Method and apparatus for measuring parameters of an electronic system

Jitter measuring equipment includes timing recovery circuitry with a first filter having a Gaussian-family response to enable the equipment to tolerate relatively long runs of data symbols of a single value without affecting the accuracy of timing of clock recovery. Potential distortion of the jitter measurement which could arise from this amplitude response characteristic is alleviated by applying the demodulated baseband signal, prior to jitter measurement, to a demodulated filter having an amplitude response characteristic that is approximately the inverse of the response of the first filter.

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Edinburgh, United Kingdom

David Taylor