Visual Information Technologies, Inc.

Viewcast.com, Inc.

Pixel Semiconductor, Inc.

David T Stoner

Michael K Corry

John P Norsworthy

David M Pfeiffer

Jay A Thompson

James A Fontaine

Dwight D Dipert

Mark Hershey

Rick Southerland

A streaming media encoder for encoding and delivering media content is disclosed. The streaming media encoder has a media input interface for receiving a media stream, a media encoder for receiving the media stream from the input interface and encoding the media stream, thereby producing an encoded media stream. The media encoder has a first confidence monitor for displaying a video image from the received media stream, a second confidence monitor for displaying a video image from the encoded media stream, and a network interface for providing the encoded media stream to a network.

Streaming media encoder with front panel control interface

There is disclosed a system and method of controlling the timing in a system having a number of different elements, each requiring individual timing signals. The system utilizes a RAM memory divided into a number of groups or cycle types, each cycle type having a number of addressable words. The individual bits of each word serve to control the individual system elements. The memory is programmed to allow each group of words to control the system timing in a different manner. Provision is made for the memory to skip certain words in a particular group under control of externally provided signals.

Memory controller flexible timing control system and method

There is disclosed a memory controller for controlling addresses to a plurality of different memory types while treating the memory system as a whole so as to create a unified addressing arrangement. The controller is structured to allow for a reprogramming of the split address between the memories and for maintaining contiguously addressed locations. A register is used to hold the split address and the register can be updated at initialization to vary the split depending upon physical memory changes. The controller also maintains a common bit length addressing word regardless of the memory size being addressed by the system processor.

Image memory controller for controlling multiple memories and method of

An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data. The pixel data output by the video processor (106) is further processed through look-up tables (108) to provide red, green and blue color signals for output to a video monitor (28). Overlay data is stored in an overlay memory plane (90), and is processed by an associated overlay data processor (80) and a video output overlay processor (116). A window clipping circuitry monitors the memory addresses from the image algorithm processor (66) to determined whether one or more pixels of a multi-pixel word are located outside of a window.

High speed image processing computer with overlapping windows-div

An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) assocated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data. The pixel data output by the video processor (106) is further processed through look-up tables (108) to provide red, green and blue color signals for output to a video monitor (28). Overlay data is stored in an overlay memory plane (90), and is processed by an associated overlay data processor (80) and a video output overlay processor (116). Mask data is generated by a mask processor coupled to the image algorithm processor (66) for masking one or more pixels in a multi-pixel word and further for masking individual bits within said pixels.

High speed image processing computer

Disclosed is an image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data. The pixel data output by the video processor (106) is further processed through look-up tables (108) to provide red, green and blue color signals for output to a video monitor (28). Overlay data is stored in an overlay memory plane (90), and is processed by an associated overlay data processor (80) and a video output overlay processor (116). The overlay processor is operable to generate page addresses to the color look-up tables responsive to image data in the overlay memory plane.

An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data. The pixel data output by the video processor (106) is further processed through look-up tables (108) to provide red, green and blue color signals for output to a video monitor (28). Overlay data is stored in an overlay memory plane (90), and is processed by an associated overlay data processor (80) and a video output overlay processor (116).

High speed image processing system using separate data processor and

Disclosed is an image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data. The pixel data output by the video processor (106) is further processed through look-up tables (108) to provide red, green and blue color signals for output to a video monitor (28). Overlay data is stored in an overlay memory plane (90), and is processed by an associated overlay data processor (80) and a video output overlay processor (116). An error correction circuit is operable to detect and correct faulty data transferred between the image memory planes and their respective data processors.

Growing community of inventors

McKinney, TX, United States of America

David T Stoner