International Business Machines Corporation

David T Shen

Richard B Booth

Janet E Poetzinger

Bradley S Gremban

Robert H Gephard

Robert R Shaw

Klaus K Maass

Hormazdyar M Dalal

Arnold Weinberger

Frank A Montegari

James M Oberschmidt

Samuel R Levine

Allen J Arnold

Robert A Miller

Michael E Bariether

Robert C Letteney

Shin-Wu Chiang

A method of clocking integrated circuit chips. A pulsed laser striking an integrated circuit module substrate is diffused through the substrate and exits the opposite surface as diffused light pulses. An integrated circuit chip mounted on the top surface of the substrate has optical receivers. The optical receivers receive pulsed energy from the diffused light pulses, converting pulsed light to electrical pulses that clock the chip.

Method of clocking integrated circuit chips

A multilayer, high yield and high density integrated circuit (IC) chips interposer and the method of manufacture therefore. A thin polyimide film is circuitized with copper on both sides. One side may be reserved for power or ground with the opposite side being a signal plane. Adhesive is laminated over both sides covering the circuit patterns. Vias are drilled through at least one adhesive surface, and through the polyimide film. Metal (copper) is blanket sputtered to coat the via walls. Polymer Metal Conductive (PMC) paste is screened to at least partially fill the vias. The Blanket metal is sub-etched using the screened PMC as a mask. Layers are stacked to form the interposer with the PMC bonding the stacked layers together and electrically interconnecting between layers.

Parallel process interposer (PPI)

Method of fabricating a multi-layer integrated circuit chip interposer

A method of replacing IC chip package wiring having an interposer comprising removing an interposer having a plurality of adhesively laminated interposer layers from the package, delaminating and replacing at least one interposer layer with a corrected interposer layer, relaminating the interposer layers with adhesive thus producing a replacement interposer and remounting the replacement interposer to the IC chip package.

Method for replacing IC chip package interposer

An apparatus for converting a multidigit decimal number into a binary number. In a preferred embodiment, the apparatus includes a register for holding the multidigit decimal number; first conversion logic, coupled to the register, for simultaneously converting a first pair of decimal digits in the multidigit decimal number, into a first binary representation and second conversion logic, coupled to said first conversion logic and the register, for simultaneously converting a second pair of decimal digits in the multidigit decimal number and the first binary representation into a second binary representation of a decimal number defined by the first and second pair of decimal digits.

Reduced execution time convert to binary circuit

An essentially symmetrical ratio decoder which covers all areas in both the positive and negative regions with only a small number of noted exceptions. Multiple boundaries were selected such that the positive and negative regions were symmetrical with only a small number of exceptions. Using these boundaries, an essentially symmetrical, unified ratio decoder was constructed using only about one-half of the integrated circuit real estate of conventional ratio decoder pairs. By decoding the sign bit from the ratio decoder adder, the ratio decoder recognizes the exceptional areas and handles them accordingly.

Improved ratio decoder for use in a non-restoring binary division circuit

Disclosed is a multilayer capacitor consisting of a plurality of laminae with each of the laminae including a conductive plate portion and a non-conductive sheet portion. The conductive plate portion has at least one tab projecting to at least one edge of the conductive plate portion with the maximum number of tabs per conductive plate portion being limited to avoid excessive lateral congestion. The laminae are divided into different groups with the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the location of the tabs. The laminae are interleaved so that:

Multilayer capacitor

A high speed multiply apparatus minimizes latch requirements and I/O pin requirement between chips by a new configuration which iteratively adds four multiples of a multiplicand in a stage of 4-2 carry save adders which then feed four-bit parallel adders each having four sum outputs and a carry output from the highest order bit position. Only the sum outputs are latched and then fed to a carry propagate adder on each iteration for addition to the previous partial products. Only the single carry output from each of the 4-bit parallel adders needs to be latched and then fed to another 4-bit parallel adder.

Growing community of inventors

Poughkeepsie, NY, United States of America

David T Shen