Semiconductor Components Industries, LLC

Lsi Logic Corporation

Lsi Corporation

Other

David T Price

Jeffrey P Gambino

Peter Austin Burke

Derryl D J Allman

Hemanshu D Bhatt

Bruce Greenwood

David Pritchard

Kyle Thomas

Rusty Winzenread

Charles E May

Byung-Sung Kwak

Sey-Shing Sun

Rick Carlton Jerome

Jeffery Allen Neuls

Gordon M Grivna

Marc Allen Sulfridge

Richard A Mauritzson

Sungkwon C Hong

Angel L Rodriguez

Kevin McStay

Jayashree Kalpathy-Cramer

Derryl J Allman

Rick Mauritzson

Michael Gerard Keyes

Kenneth Andrew Bates

Ryan Rettmann

Robi Banerjee

Dean E Probst

Tomas Geurts

Manuel H Innocent

Mark Griswold

Bigildis Dosdos

Radim Mlcousek

Mark Ward

Arash Elhami Khorasani

Santosh Menon

Martin Kejhar

Kevin Alexander Stewart

An imaging device may include single-photon avalanche diodes (SPADs). To mitigate crosstalk, isolation structures may be formed around each SPAD. The isolation structures may include front side deep trench isolation structures that extend partially or fully through a semiconductor substrate for the SPADs. The isolation structures may include a metal filler such as tungsten that absorbs photons. The isolation structures may include a p-type doped semiconductor liner to mitigate dark current. The isolation structures may include a buffer layer such as silicon dioxide that is interposed between the metal filler and the p-type doped semiconductor liner. The isolation structures may have a tapered portion or may be formed in two steps such that the isolation structures have different portions with different properties. An additional filler such as polysilicon or borophosphosilicate glass may be included in some of the isolation structures in addition to the metal filler.

Semiconductor devices with single-photon avalanche diodes and isolation structures

Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

Edge seals for semiconductor packages

Implementations of a semiconductor device may include a photodiode included in a second epitaxial layer of a semiconductor substrate; light shield coupled over the photodiode; and a first epitaxial layer located in one or more openings in the light shield. The first epitaxial layer and the second epitaxial layer may form a single crystal.

Global shutter sensor systems and related methods

Implementations of image sensor devices may include a through-silicon-via (TSV) formed in a backside of an image sensor device and extending through a material of a die to a metal landing pad. The metal landing pad may be within a contact layer. The devices may include a TSV edge seal ring surrounding a portion of the TSV in the contact layer and extending from a first surface of the contact layer into the contact layer to a depth coextensive with a depth of the TSV.

Backside illumination image sensors

In one embodiment, a method of forming a semiconductor device may include forming a sense resistor to receive a high voltage signal and form a sense signal that is representative of the high voltage signal. An embodiment of the sense resistor may optionally be formed overlying a polysilicon resistor. The method may also have an embodiment that may include forming a plurality of capacitors in parallel to portions of the sense resistor wherein the plurality of capacitors are connected together in series.

Method of forming a semiconductor device

A stacked assembly of semiconductor devices includes a mounting pad covering a first portion of a low-side semiconductor device, and a contact layer covering a second portion of the low-side semiconductor device. A first mounting clip electrically connected to the contact layer has a supporting portion joining the first mounting clip to a first lead frame portion. A second mounting clip attached to the mounting pad has a supporting portion joining the second mounting clip to a second lead frame portion. A high-side semiconductor device has a first terminal electrically connected to the first mounting clip and thereby to the contact layer, and a second terminal electrically connected to the second mounting clip.

Stacked transistor assembly with dual middle mounting clips

Implementations of image sensors may include a first die including an image sensor array and a first plurality of interconnects where the image sensor array includes a plurality of photodiodes and a plurality of transfer gates. The image sensor array may also include a second die including a second plurality of interconnects and a plurality of capacitors, each capacitor selected from the group consisting of deep trench capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and 3D stacked capacitors. The first die may be coupled to the second die through the first plurality of interconnects and through the second plurality of interconnects. No more than eight photodiodes of the plurality of photodiodes of the first die may be electrically coupled with no more than four capacitors of the plurality of capacitors.

Stacked image sensor capacitors and related methods

An image sensor structure includes a region of semiconductor material having a first major surface and a second major surface. A pixel structure is within the region of semiconductor material and includes a plurality of doped regions and a plurality of conductive structures. A metal-filled trench structure extends from the first major surface to the second major surface. A first contact structure is electrically connected to a first surface of the conductive trench structure, and a second contact structure electrically connected to a second surface of the conductive trench structure. In one embodiment, the second major surface is configured to receive incident light.

Semiconductor image sensor structure having metal-filled trench contact

In one embodiment, a method for forming a backside illuminated image sensor includes providing a region of semiconductor material having a first major surface and a second major surface configured to receive incident light. A pixel structure is formed within the region of semiconductor material adjacent the first major surface. Thereafter, a trench structure comprising a metal material is formed extending through the region of semiconductor material. A first surface of the trench structure is adjacent the first major surface of the region of semiconductor material and a second surface adjoining the second major surface of the region of semiconductor material. A first contact structure is electrically connected to one surface of the conductive trench structure and a second contact structure is electrically connected to an opposing second surface.

Method for forming a semiconductor image sensor device

A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.

Spacer-less transistor integration scheme for high-K gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe and strained silicon schemes

Growing community of inventors

Gresham, OR, United States of America

David T Price