International Business Machines Corporation

Globalfoundries Inc.

David T Hui

Steven H Voldman

Xiaobin Yuan

Alan J Drake

Pawel Owczarczyk

Marshall Dale Tiner

Michael Stephen Floyd

Alan Bernard Botula

Otto Andreas Torreiter

Francesco A Campisano

Joseph E Eckelman

Ulrich Baur

Robert Russell Williams

Charles B Winn

Benjamin W Mashak

Haluk O Askin

Bijan Salimi

An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.

Multi-core dynamic frequency control system

A circuit for monitoring and controlling a clock signal generated by a clock source in a microprocessor device may include a voltage divider network that provides a plurality of voltages, a selector device that receives the plurality of voltages and provides a scaled supply voltage and a scaled ground voltage from the plurality of voltages, and at least one delay element that receives the scaled supply voltage and the scaled ground voltage and generates a delayed pulse signal by applying a delay to each pulse of the clock signal. The delayed pulse signal may include a delay magnitude that is controllable by the scaled supply voltage and the scaled ground voltage, such that the delayed pulse signal is used to generate a frequency correction signal based on a variation to a supply voltage of the microprocessor. The frequency correction signal may then be applied to the clock source.

Reconfigurable circuit to emulate system critical paths

A digitally-controlled oscillator includes a base frequency generator having an odd number of base inverters connected end-to-end to generate an output signal that oscillates at a predetermined frequency and a frequency-adjusting unit connected to the base frequency generator. The frequency-adjusting unit includes a first string of switchable inverters connected in series with each other, the switchable inverters having sizes that decrease from an input end of the first string to the output end of the first string.

Progressively sized digitally-controlled oscillator

The present invention relates to a test for current leakage of driver/receiver stages, and in particular for bi-directional input/output stages ( ) of a semiconductor chip. Two dedicated support transistor devices ( ) are added into the prior art switching scheme, together with a simple control logic ( ) for selectively controlling the two dedicated support transistor devices according to a predetermined test scheme. An on-chip self-test feature provides valid voltage levels which are convertible by the receiver ( ) to predictable logic states at the evaluation line RDATA. The test can be performed autonomously on the chip without the requirement for an external test device.

Self-test for leakage current of driver/receiver stages

The present invention relates to a method and system for full parametric testing of the drive and receive capability of bi-directional driver/receiver-stages, and in particular of bi-directional input/output-stages of a semiconductor chip. Electrical properties, as for example DC-resistance, AC-impedance of a driver stage are tested by at least one test load implemented on the chip itself which causes a characteristic voltage drop usable for test evaluation. Advantageously, the output stage devices of P-type ( ) and N-type ( ), respectively, are split into at least two sub-devices P , P and N , N , and are controlled separately by a control logic ( ). Then, for example N is used for testing the P device, and P is used for testing the N-device. Thus, devices already present on the chip are re-used for test purposes, which makes off-chip testing unnecessary.

Self-test with split, asymmetric controlled driver output stage

An ESD clamping circuit arranged in a darlington configuration and constructed from SiGe or similar type material. The ESD clamping circuit includes additional level shifting circuitry in series with either the trigger or clamping device or both, thus allowing non-native voltages that exceed the BVCEO of the trigger and/or clamp devices.

Electrostatic discharge power clamp circuit

A SiGe ESD power clamp in a Darlington type configuration where the trigger device has a collector-to-emitter breakdown voltage (BVCEO) that is lower than that of the clamping device, and a frequency cutoff that is higher than that of the clamping device.

A terminator circuit for connection to a network can be fabricated and used within CMOS-SOI (complementary metal oxide semiconductor&mdash;silicon on insulator) for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit. The reference circuit has SOI devices back to back source coupled CMOS-SOI devices to each other for a tuned center reference voltage node, with their bodies connect to upper and lower level power supplies respectively. An upper level power source is connected to one side of the reference voltage node and a lower reference voltage power source is connected to the other side of the reference voltage node. The voltage level above the common tuned reference voltage and a lower level voltage is supplied to the terminator's corresponding input terminal circuit control nfet and pfet mirror devices whose bodies are also connected respectively to lower and upper level supply power to control each of their turn on voltages. Resistors of the reference path establish the swing voltage of the terminator as being that approximating an ideal 50 ohm split resistor terminator.

SOI small signal terminator and network

A terminator circuit for connection to a network can be fabricated and used within CMOS-SOI (complementary metal oxide semiconductor&mdash;silicon on insulator) for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from the first circuit to the second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit and to a differential hysteresis receiver. The reference circuit has devices back to back source coupled devices to each other for a tuned center reference voltage node. An upper level power source is connected to one side of the reference voltage node and a lower reference voltage power source is connected to the other side of the reference voltage node. The voltage level above the common tuned reference voltage and a lower level voltage is supplied to the terminator's corresponding input terminal circuit control nfet and pfet mirror devices also connected respectively to lower and upper level supply power to control each of their turn on voltages. Resistors of the reference path establish the swing voltage of the terminator as being that approximating an ideal 50 ohm split resistor terminator. The tuned voltage levels supplied to the terminator input circuit for the termination to the network as a terminator on the data line passing data from said first circuit to said second circuit supplying, and also, supplied to the hysteresis differential receiver which is integrated into the terminator circuit to set up a threshold tuned reference voltage between the logic levels of said terminator input circuit for the network.

CMOS small signal terminated receiver

CMOS small signal switchable impedence and voltage adjustable terminator with an integrated hysteresis receiver network for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit. The reference circuit has devices back to back source coupled devices to each other for a tuned center reference voltage node, with their bodies connect to upper and lower level power supplies respectively. An upper level power source is connected to one side of the reference voltage node and a lower reference voltage power source is connected to the other side of the reference voltage node. The voltage level above the common tuned reference voltage and a lower level voltage is supplied to the terminator's corresponding input terminal circuit control nfet and pfet mirror devices whose bodies are also connected respectively to lower and upper level supply power to control each of their turn on voltages. The reference path establishes,the swing voltage of the terminator as being that approximating an ideal 50 ohm split resistor terminator. An adjustment section provides an impedance adjustment and an adjustment circuits for tuning the center voltage of the incoming voltage swing up and down. A integrated hysteresis receiver forms part of the terminator/circuit and is coupled to the network input terminal for connecting the network's first circuit to the network's second circuit.

CMOS small signal switchable impedence and voltage adjustable terminator with hysteresis receiver network

A terminator circuit for connection to a network can be fabricated and used within CMOS-SOI (complementary metal oxide semiconductor&mdash;silicon on insulator) for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit. The reference circuit has SOI devices back to back source coupled CMOS-SOI devices to each other for a tuned center reference voltage node, with their bodies connect to upper and lower level power supplies respectively. An upper level power source is connected to one side of the reference voltage node and a lower reference voltage power source is connected to the other side of the reference voltage node. The voltage level above the common tuned reference voltage and a lower level voltage is supplied to the terminator's corresponding input terminal circuit control nfet and pfet mirror devices whose bodies are also connected respectively to lower and upper level supply power to control each of their turn on voltages. Resistors of the reference path establish the swing voltage of the terminator as being that approximating an ideal 50 ohm split resistor terminator. A terminator inhibit control input circuit is coupled to the reference circuit and input circuit's to enable and disable the terminator network with a switching control signal. One or more terminal circuit adjustment sections enable one or more levels of impedance adjustment.

CMOS small signal switchable adjustable impedence terminator network

Method of use with a terminator and network

A CMOS terminator circuit for connection to a network can be fabricated and used within for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit. The reference circuit has SOI devices back to back source coupled devices to each other for a tuned center reference voltage node, with their bodies connect to upper and lower level power supplies respectively. An upper level power source is connected to one side of the reference voltage node and a lower reference voltage power source is connected to the other side of the reference voltage node. The voltage level above the common tuned reference voltage and a lower level voltage is supplied to the terminator's corresponding input terminal circuit control nfet and pfet mirror devices whose bodies are also connected respectively to lower and upper level supply power to control each of their turn on voltages. The reference path swing voltage of the terminator is established as being that approximating an ideal 50 ohm split resistor terminator. An adjustment section enables the voltage to be adjusted up and down to re-center the An adjustment section enables adjustment of the impedance of the terminator, with fine tuning of the terminator to a desired reflection for the nets and adjustment of the center voltage which allows tune out of any process mistracking and re-centering of the terminator voltage, so that maximum input signal voltages can be obtained without creating skew between the zero and one logic levels.

CMOS small signal switchable, impedence and voltage adjustable terminator network

A terminator circuit for connection to a network can be fabricated and used within CMOS (complementary metal oxide semiconductor) for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit. The reference circuit has SOI devices back to back source coupled CMOS-SOI devices to each other for a tuned center reference voltage node, with their bodies connect to upper and lower level power supplies respectively. An upper level power source is connected to one side of the reference voltage node and a lower reference voltage power source is connected to the other side of the reference voltage node. The voltage level above the common tuned reference voltage and a lower level voltage is supplied to the terminator's corresponding input terminal circuit control nfet and pfet mirror devices each of their turn on voltages. Resistors of the reference path establish the swing voltage of the terminator as being that approximating an ideal 50 ohm split resistor terminator.

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Poughkeepsie, NY, United States of America

David T Hui