Netlogic Microsystems, Inc

Rmi Corporation

Juniper Networks, Inc.

Broadcom Corporation

Intel Corporation

David T Hass

Abbas Rashid

Nazar A Zaidi

Ramesh Panwar

Gaurav Garg

Robert G Hathaway

Ricardo Ramirez

Kaushik Kuila

Julianne Zhu

Frederick R Gruner

Mark Vilas

Elango Ganesan

Michael Freed

Ahmed Shahid

Fred Gruner

Yen C Lee

Mark Bryers

Sankar Ramanoorthi

John Phillips

Yuhong Zhou

Gregory G Spurrier

Basab Mukherjee

Chau Anh Ngoc Nguyen

Robert Laker

Harshvardhan P Sharangpani

Michael Paul Corwin

Gaurav Singh

Luke E Girard

Ken Arora

Syed Reza

Chau Ahn Ngoc Nguyen

Rohini Krishna Kaza

Ramesh Penwar

An apparatus and method are provided for allocating a plurality of packets to different processor threads. In operation, a plurality of packets are parsed to gather packet information. Additionally, a parse operation is performed utilizing the packet information to generate a key, and a hash algorithm is performed on this key to produce a hash. Further, the packets are allocated to different processor threads, utilizing the hash or the key.

System and method for parsing and allocating a plurality of packets to processor core threads

A system, method, and computer program product are provided for conditionally sending a request for data to a node based on a determination. In operation, a first request for data is sent to a cache of a first node. Additionally, it is determined whether the first request can be satisfied within the first node, where the determining includes at least one of determining a type of the first request and determining a state of the data in the cache. Furthermore, a second request for the data is conditionally sent to a second node, based on the determination.

System, method, and computer program product for conditionally sending a request for data to a node based on a determination

Disclosed is an approach for implementing a flexible parser for a networking system. A micro-core parser is implemented to process packets in a networking system. The micro-cores of the parser read the packet headers, and perform any suitably programmed tasks upon those packets and packet headers. One or more caches may be associated with the micro-cores to hold the packet headers.

Programmable micro-core processors for packet parsing

An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Method and apparatus for implementing cache coherency of a processor

Disclosed is an approach for implementing a flexible parser for a networking system. A micro-core parser is implemented to process packets in a networking system. The micro-cores of the parser read the packet headers, and perform any suitably programmed tasks upon those packets and packet headers. One or more caches may be associated with the micro-cores to hold the packet headers. A dependency list is used to maintain proper ordering of packets being processed by the micro-cores.

Programmable micro-core processors for packet parsing with packet ordering

Advanced processor with fast messaging network technology

A system, method, and computer program product are provided for sending a message from a first queue to a second queue associated with a receiver agent in response to a request. In operation, a message is sent from a sender agent to a first queue. Additionally, a request is received at the first queue from a receiver agent. Furthermore, the message is sent from the first queue to a second queue associated with the receiver agent, in response to the request.

System, method, and computer program product to distribute workload

Advanced processor translation lookaside buffer management in a multithreaded system

Advanced processor with interfacing messaging network to a CPU

A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.

Content service aggregation system

A method and system are provided for performing efficient and effective scheduling in a multi-threaded system. Dynamic control of scheduling is provided, in which priority weights can be assigned for some or all of the threads in the multi-threaded system. The priority weights are employed to control prioritization of threads and thread instructions by a scheduler. An instruction count for each thread is used in combination with the priority weights to determine the prioritization order in which instructions are fetched and assigned to execution units for processing.

Weighted instruction count scheduling

A processor includes a plurality of processor cores, a networking output, and a packet ordering device. The packet ordering device determines an ordering for packets that are processed by the processor cores. The packets are released to the networking output in a determined order.

Processor with packet ordering device

Systems, apparatusses, and methods are disclosed for improving performance of a stride-based prefetcher on an out-of-order central processing unit (CPU). The present disclosure teaches a processor system that employs out-of-order stride prefetch units. The out-of-order stride prefetch units are utilized for issuing prefetches for out-of-order stride access patterns. In one or more embodiments, the out-of-order stride prefetch units examine the offsets between past virtual address (VA) accesses and the directions of the past VA accesses in order to generate an estimate of the underlying VA access stride of the executed program code (PC). In at least one embodiment, the out-of-order stride prefetch units use the estimate of the VA access stride in order to generate a prediction of future VA accesses. In some embodiments, after the out-of-order stride prefetch units have generated the prediction of future VA accesses, the out-of-order stride prefetch units prefetch the predicted future VA accesses.

Performance of a stride-based prefetcher on an out-of-order processing unit (CPU)

An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Messaging network for processing data using multiple processor cores

An improved approach is described for implementing a clock management system. A multi-part phase locked loop circuit is provided to handle the different clock needs of the circuit, where each of the phase locked loops within the multi-part phase locked loop circuit may feed a clock output to one or more divider circuits. The divider circuits may be dedicated to specific components. For example, a SoC PLL may generate a clock output to a SoC divider that is dedicated to providing a clock to content address memory (CAM) components. This approach allows the clock management system to efficiently generate clock signals with variable levels of frequencies, even for complicated circuits having many different functional portions and components.

Multi-part clock management

Growing community of inventors

Santa Clara, CA, United States of America

David T Hass