Microsoft Technology Licensing, LLC

Advanced Micro Devices Corporation

David T Harper

Eric Clarence Peterson

Gagan Gupta

Douglas Christopher Burger

Aaron L Smith

Antony Ian Taylor Rowstron

Austin N Donnelly

Stephen Francis Heil

Shobana Balakrishnan

Mark Santaniello

Adam B Glass

Sergey Legtchenko

David Alex Butler

Darko Kirovski

Burton Jordan Smith

Brett A Tischler

Carl D Dietz

Ji Yong Shin

David F Bremner

Mark A Santaniello

Systems and methods are disclosed for performing wide memory operations for a wide data cache line. In some examples of the disclosed technology, a processor having two or more execution lanes includes a data cache coupled to memory, a wide memory load circuit that concurrently loads two or more words from a cache line of the data cache, and a writeback circuit situated to send a respective word of the concurrently-loaded words to a selected execution lane of the processor, either into an operand buffer or bypassing the operand buffer. In some examples, a sharding circuit is provided that allows bitwise, byte-wise, and/or word-wise manipulation of memory operation data. In some examples, wide cache loads allows for concurrent execution of plural execution lanes of the processor.

Coupling wide memory interface to wide write back paths

Systems and methods are disclosed for executing instructions with a block-based processor. Instructions can be executed in any order as their dependencies arrive, but the individual instructions are committed in a serial fashion. Further, exception handling can be performed by storing transient state for an instruction block and resuming by restoring the transient state. This allows programmers to see intermediate state for the instruction block before the subject block has committed. In one examples of the disclosed technology, a method of operating a processor executing a block-based instruction set architecture includes executing at least one instruction encoded for an instruction block, responsive to determining that an individual instruction of the instruction block can commit, advancing a commit frontier for the instruction block to include all instructions in the instruction block that can commit, and committing one or more instructions inside the advanced commit frontier.

Commit logic and precise exceptions in explicit dataflow graph execution architectures

A data center includes a plurality of computing units that communicate with each other using wireless communication, such as high frequency RF wireless communication. The data center may organize the computing units into groups (e.g., racks). In one implementation, each group may form a three-dimensional structure, such as a column having a free-space region for accommodating intra-group communication among computing units. The data center can include a number of features to facilitate communication, including dual-use memory for handling computing and buffering tasks, failsafe routing mechanisms, provisions to address permanent interface and hidden terminal scenarios, etc.

Computing units using directional wireless communication

A direct network is described in which each resource is connected to a switching fabric via a set of two or more routing nodes. The routing nodes are distributed so as to satisfy at least one inter-node separation criterion. In one case, the separation criterion specifies that, for each resource, a number of routing nodes that share a same coordinate value with another routing node in the set (in a same coordinate dimension) is to be minimized. In some network topologies, such as a torus network, this means a number of unique loops of the direct network to which each resource is connected is to be maximized. The routing provisions described herein offer various performance benefits, such as improved latency-related performance.

Direct network having plural distributed connections to each resource

Low cost storage for write once read rarely data is described. In an embodiment a storage device comprises a plurality of hard disk drives connected to a server via an interconnect fabric. The storage device comprises a cooling system which is only capable of cooling a first subset of the hard disk drives and a power supply system which is only capable of powering a second subset of the hard disk drives and in some examples, the interconnect fabric may be only capable of providing full bandwidth for a third subset of the hard disk drives. Each subset may comprise only a small fraction of hard disk drives. A control mechanism, which may be implemented in software, is provided which controls which hard disk drives are active at any time in order that the constraints set by the cooling and power supply systems and interconnect fabric are not violated.

Low cost storage for rarely read data

A substantially cable-free board connection assembly may include a plurality of printed circuit boards (PCBs) forming an interconnect plane for a plurality of electronic devices respectively attached to a plurality of plane boards included in the interconnect plane. An insertion direction for substantially all connectors is substantially perpendicular to a face of the interconnect plane. At least a portion of the board connection assembly is mounted to a support structure via a flexible connection.

Substantially rigid interconnection structure for devices

A low-overhead conditional synchronization instruction operates on a synchronization variable which includes a lock bit, a state specification, and bits for user-defined data. The instruction specifies the memory address of the synchronization variable and a condition. During the synchronization instruction the condition is compared to the state specification within an atomic region. The match succeeds if the condition matches the state specification and the lock bit is clear. The synchronization instruction may operate with a cache under a cache coherency protocol, or without a cache, and may include a timeout operand.

Low-level conditional synchronization support

A highly integrated multimedia processor employs a shared cache between tightly coupled central processing and graphics units to provide the graphics unit access to data retrieved from system memory or data processed by the central processing unit before the data is written-back or written-through to system memory, thus reducing system memory bandwidth requirements. Regions in the shared cache can also be selectively locked down thereby disabling eviction or invalidation of a selected region, to provide the graphics unit with a local scratchpad area for applications such as, but not limited to, temporary video line buffering storage for filter applications and composite buffering for blending texture maps in multi-pass rendering.

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Seattle, WA, United States of America

David T Harper