Movidius Limited

Intel Corporation

David T Bernard

Niall Hanrahan

Fergal Connor

Kevin Brady

Martin Power

Martin-Thomas Grymel

Cormac Brick

Gary Baugh

Derek Harnett

Peter McGlynn

Valentina Rigo

Nicholas Paul Cowley

Ruchir Saraswat

Richard J Goldman

Gordon J Walsh

Michael Langan

Methods, apparatus, systems and articles of manufacture are disclosed for sparse tensor storage for neural network accelerators. An example apparatus includes sparsity map generating circuitry to generate a sparsity map corresponding to a tensor, the sparsity map to indicate whether a data point of the tensor is zero, static storage controlling circuitry to divide the tensor into one or more storage elements, and a compressor to perform a first compression of the one or more storage elements to generate one or more compressed storage elements, the first compression to remove zero points of the one or more storage elements based on the sparsity map and perform a second compression of the one or more compressed storage elements, the second compression to store the one or more compressed storage elements contiguously in memory.

Methods and apparatus for sparse tensor storage for neural network accelerators

Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.

Systems, apparatus, and methods to debug accelerator hardware

Methods, apparatus, systems and articles of manufacture to compress data are disclosed. An example apparatus includes a data slicer to split a dataset into a plurality of blocks of data; a data processor to select a first compression technique for a first block of the plurality of blocks of data based on first characteristics of the first block; and select a second compression technique for a second block of the plurality of blocks of data based on second characteristics of the second block; a first compressor to compress the first block using the first compression technique to generate a first compressed block of data; a second compressor to compress the second block using the second compression technique to generate a second compressed block of data; and a header generator to generate a first header identifying the first compression technique and a second header identifying the second compression technique.

Methods and apparatus to compress data

Methods, apparatus, systems, and articles of manufacture are disclosed that increase data reuse for multiply and accumulate (MAC) operations. An example apparatus includes a MAC circuit to process a first context of a set of a first type of contexts stored in a first buffer and a first context of a set of a second type of contexts stored in a second buffer. The example apparatus also includes control logic circuitry to, in response to determining that there is an additional context of the second type to be processed in the set of the second type of contexts, maintain the first context of the first type in the first buffer. The control logic circuitry is also to, in response to determining that there is an additional context of the first type to be processed in the set of the first type of contexts maintain the first context of the second type in the second buffer and iterate a pointer of the second buffer from a first position to a next position in the second buffer.

Methods, apparatus, and articles of manufacture to increase data reuse for multiply and accumulate (MAC) operations

Methods, apparatus, systems and articles of manufacture to store and access multi-dimensional data are disclosed. An example apparatus includes a memory; a memory allocator to allocate part of the memory for storage of a multi-dimensional data object; and a storage element organizer to: separate the multi-dimensional data into storage elements; store the storage elements in the memory, the stored storage elements being selectively executable; store starting memory address locations for the storage elements in an array in the memory, the array to facilitate selectable access of data of the stored elements; store a pointer for the array into the memory.

Methods and apparatus to store and access multi-dimensional data

Methods, apparatus, systems and articles of manufacture to perform dot product calculations using sparse vectors are disclosed. An example apparatus includes means for generating a mask vector based on a first logic operation on a difference vector and an inverse of a control vector, the control vector based on a first bitmap of a first sparse vector and a second bitmap of a second sparse vector; means for generating a first product of a third value from the first sparse vector and a fourth value from the second sparse vector, the third value based on (i) the mask vector and (ii) a second sparsity map based on the first sparse vector, the fourth value corresponding to (i) the mask vector and (ii) a second sparsity map corresponding to the second sparse vector; and means for adding the first product to a second product of a previous iteration.

Dot product calculators and methods of operating the same

Methods, apparatus, systems and articles of manufacture to compress data are disclosed. An example apparatus includes an off-chip memory to store data; a data slicer to split a dataset into a plurality of blocks of data; a data processor to select a first compression technique for a first block of the plurality of blocks of data based on first characteristics of the first block; and select a second compression technique for a second block of the plurality of blocks of data based on second characteristics of the second block; a first compressor to compress the first block using the first compression technique to generate a first compressed block of data; a second compressor to compress the second block using the second compression technique to generate a second compressed block of data; a header generator to generate a first header identifying the first compression technique and a second header identifying the second compression technique; and an interface to transmit the first compressed block of data with the first header and the second compressed block of data with the second header to be stored in the off chip memory.

Methods and apparatus to store and access multi dimensional data

Methods, apparatus, systems and articles of manufacture to perform dot product calculations using sparse vectors are disclosed. An example dot product calculator includes a first logic AND gate to perform a first logic AND operation with a first input vector and a second input vector, the first logic AND gate to output a control vector; a second logic AND gate to perform a second logic AND operation with a difference vector and an inverse of the control vector, the second logic AND gate to output a mask vector; a third logic AND gate to output a first vector; a first counter to generate a first ones count based on a first total number of ones of the first vector; a fourth logic AND gate to output a second vector; a second counter to generate a second ones count; and a multiplier to generate a product.

Methods, apparatus, systems and articles of manufacture to perform dot product calculations using sparse vectors are disclosed. An example dot product calculator includes a counter to determine a trailing binary count of a control vector, the control vector corresponding to a first result of a first logic AND operation on a first bitmap of a first sparse vector and a second bitmap of a second sparse vector. The example dot product calculator further includes a mask generator to generate a mask vector based on the trailing binary count. The example dot product calculator further includes an interface to access a first value of the first sparse vector based on a second result of a second logic AND operation on the first bitmap and the mask vector and access a second value of the second sparse vector based on a third result of a third logic AND operation on the second bitmap and the mask vector. The example dot product calculator further includes a multiplier to multiply the first value with the second value to generate a product.

In at least one embodiment there is provided a method for managing bulk capacitance of a power supply system. The method includes precharging first and second bulk capacitors of the power supply system to approximately a first output voltage level and a second output voltage level, respectively; receiving a first command signal to generate, by the power supply, the first output voltage level; coupling the first bulk capacitance to load circuitry coupled to the power supply; receiving a second command signal to generate, by the power supply, the second output voltage level; and coupling the second bulk capacitance to the load circuitry coupled to the power supply.

Techniques for power supply topologies with capacitance management to reduce power loss associated with charging and discharging when cycling between power states

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Ieixlip, Ireland

David T Bernard