Kingston Technology Corporation

David Sun

Ramon S Co

Ben Wei Chen

Tat Leung Lai

David Hong-Dien Chen

Ngoc V Le

Mike Chen

George Shiu

Choon-Tak Tang

Chin-Tang Yen

George K L Shiu

A management hub is disclosed. The management hub comprises an interface; a master hub controller coupled to the interface; a plurality of ports coupled to the master hub controller; a microcontroller coupled to the master hub controller; and hub setting switch and a slave hub controller coupled to the microcontroller and the plurality of ports. The management hub also includes a memory device coupled to the microcontroller, the memory device including a hidden drive information partition and a hidden drive organizer partition for managing and identifying information in various drives coupled to the plurality of ports, wherein when the management hub is first connected to a host system the drives are displayed in an inactive state.

Managing and indentifying multiple memory storage devices

Method and system for expanding the memory capacity of devices that use flash memory cards. In one aspect, a memory card expander assembly includes an adaptor shaped to be connected to a memory card slot of a host device, and a receptacle assembly in communication with the adaptor and operative to be attached to the host device. The receptacle assembly includes an expanded memory card slot operative to connect to a memory card such that the host device can communicate with the connected memory card when the adaptor is connected to the memory card slot.

Flash memory card expander

A Flash memory card system is disclosed. The Flash memory card system comprises a Flash memory wireless host adapter and a Flash memory bus wireless device. The Flash memory wireless host adapter comprises a Flash memory card connector and a Flash memory controller coupled to the Flash memory card connector. The Flash-memory card signals are converted to standard Flash memory internal bus signals by the Flash memory controller. The host adapter further comprises a Flash memory wireless module coupled to the Flash memory controller for receiving and transmitting the standard Flash memory bus signals wirelessly. The Flash-memory bus wireless device comprises a Flash memory bus wireless device adapter coupled to a Flash memory. The device adapter is paired to the wireless module for receiving and transmitting the standard Flash memory bus signals wirelessly. A host device storage capacity utilizing the Flash memory card system is expanded.

Wireless flash memory card expansion system

A Flash memory controller is disclosed. The Flash memory controller comprises a host interface, a Flash memory interface, controller logic coupled between the host interface, the controller logic handling a plurality of voltages. The controller also includes a mechanism for allowing a multiple voltage host to interface with a high voltage or a multiple voltage Flash memory. A multiple voltage Flash memory controller in accordance with the present invention provides the following advantages over conventional Flash memory controllers: (1) a voltage host is allowed to interface with multiple Flash memory components that operate at different voltages in any combination; (2) power consumption efficiency is improved by integrating the programmable voltage regulator, and voltage comparator mechanism with the Flash memory controller; (3) External jumper selection is eliminated for power source configuration; and (4) Flash memory controller power source interface pin-outs are simplified.

Flash memory controller utilizing multiple voltages and a method of use

A Flash memory controller includes a host interface, a Flash memory interface, controller logic coupled between the host interface, the controller logic handling a plurality of voltages. The controller also includes a mechanism for allowing a multiple voltage host to interface with a high voltage or multiple voltage Flash memory. A multiple voltage Flash memory controller in accordance with the present invention provides the following advantages over conventional Flash memory controllers: (1) a voltage host is allowed to interface with multiple Flash memory components that operate at different voltages in any combination; (2) power consumption efficiency is improved by integrating the programmable voltage regulator, and voltage comparator mechanism with the Flash memory controller; (3) External jumper selection is eliminated for power source configuration; and (4) Flash memory controller power source interface pin-outs are simplified.

A Flash memory controller is disclosed. The Flash memory controller comprises a host interface, a Flash memory interface, controller logic coupled between the host interface the controller logic handling a plurality of voltages. The controller also includes a mechanism for allowing a multiple voltage host to interface with a high voltage or a multiple voltage Flash memory. A multiple voltage Flash memory controller in accordance with the present invention provides the following advantages over conventional Flash memory controllers: (1) a voltage host is allowed to interface with multiple Flash memory components that operate at different voltages in any combination; (2) power consumption efficiency is improved by integrating the programmable voltage regulator, and voltage comparator mechanism with the Flash memory controller; (3) External jumper selection is eliminated for power source configuration; and (4) Flash memory controller power source interface pin-outs are simplified.

A manufacturing method makes memory modules from partially-good DRAM chips soldered to its substrate. The partially-good DRAM chips have a number of defective memory cells that is below a test threshold, such as 10%. Packaged DRAM chips are optionally pre-screened and considered to pass when the number of defects found is less than the test threshold. A defect table is created during testing and written to a serial-presence-detect electrically-erasable read-only memory (SPD-EEPROM) on the memory module. The memory module is finally tested on a target-system tester that reads the defect table during booting, and redirects memory access to defective memory locations identified by the defect table. The memory modules may be burned in or tested at various temperatures and voltages to increase reliability.

Manufacturing method for partially-good memory modules with defect table in EEPROM

A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module. The AMB fully buffers memory requests that are sent as serial packets over southbound lanes from a host. Memory-access addresses are extracted from the serial packets by the AMB. The repair controller compares the memory-access addresses to repair addresses and diverts access from defective memory chips to a spare memory for the repair addresses. The repair addresses can be located during testing of the memory module and programmed into a repair address buffer on the AMB. The repair addresses could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to the repair address buffer on the AMB during power-up.

Repairing advanced-memory buffer (AMB) with redundant memory buffer for repairing DRAM on a fully-buffered memory-module

An error-correcting fully-buffered memory module can detect and correct some errors in data read from memory chips. An error correction code ECC controller is added to the Advanced Memory Buffer (AMB) on the memory module that fully buffers memory requests sent as serial packets. The error correction controller generates ECC bits for write data, and both the ECC bits and the write data are written to the memory chips by a DRAM controller in the AMB. During reads, an ECC checker generates a syndrome and can activate an error corrector to correct data or signal a non-correctable error. The corrected data is formed into serial packets sent back to the motherboard by the AMB. Configuration data for the ECC controller could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to error-correction configuration registers on the AMB during power-up.

Fully-buffered memory-module with error-correction code (ECC) controller in serializing advanced-memory buffer (AMB) that is transparent to motherboard memory controller

Memory chips are tested by insertion into a chip test socket on a test adapter board that is mounted to the reverse or solder-side of a personal computer motherboard. A memory module socket is removed from the motherboard, and adapter pins are inserted into holes for the removed memory module socket, but from the reverse (solder) side of the motherboard. The adapter pins connect to the test adapter board either directly, through a connector plug, or through an intervening adapter board. The test adapter board has soldered onto it additional memory chips and buffer chips on a memory module, such as an Advanced Memory Buffer (AMB) for a fully-buffered memory module. The built-in-self-test (BIST) feature of the AMB may be used to test the memory chip under test in the chip test socket, or the processor on the motherboard may write and read the memory chip.

Testing DRAM chips with a PC motherboard attached to a chip handler by a solder-side adaptor board with an advanced-memory buffer (AMB)

Reliable memory modules are assembled from partially-tested memory chips that are neither individually burned-in nor fully tested. Instead, individual memory chips are partially tested to screen out gross failures and then assembled into memory modules that are inserted into memory-module burn-in boards and placed into a burn-in oven. The memory modules are stressed during burn-in by high temperatures and applied voltages. After burn-in, the memory modules are removed from the memory-module burn-in boards and extensively tested. Functional tests include many test patterns to test all memory locations in the partially-tested memory chips on the memory modules. Tests are performed at corner conditions such as high temperature and voltage. Infant mortality and single-bit faults are detected by the functional tests after module burn-in. The number of insertions into burn-in boards is reduced by the number of memory chips per module minus one, so handling and test costs are reduced.

Memory-module manufacturing method with memory-chip burn-in and full functional testing delayed until module burn-in

Repairing Advanced-Memory Buffer (AMB) with redundant memory buffer for repairing DRAM on a fully-buffered memory-module

Fully-buffered memory-module with redundant memory buffer in serializing advanced-memory buffer (AMB) for repairing DRAM

A downgraded memory module has downgraded DRAM chips soldered to its substrate. The downgraded DRAM chips have a defective memory cell in a logical quadrant of the memory. A physical MSB is a row address present on a non-downgraded DRAM of size S but not used on a downgraded DRAM size S/2. The physical MSB and a second address pin are non-multiplexed address pins that do not carry column addresses. The physical MSB and the second address pin logically divided the DRAM into quadrants. Two good quadrants without defects are selected, and jumpers on the memory module drive the physical MSB and the second address pin with signals that select only these two quadrants and disable access to quadrants containing defects. DRAM chips can be marked or sorted into bins for combinations of good quadrants. Downgraded memory modules have all DRAM chips from the same bin that share jumper settings.

Growing community of inventors

Irvine, CA, United States of America

David Sun