Integrated Device Technology, Inc.

David Stuart Gibson

Roland T Knaack

Bruce Lorenz Chin

Mario F Au

Angus David Starr MacAdam

Mario Montana

Mike Farrell

Stewart Speed

Srinivas Satish Babu Bamdhamravuri

Uksong Kang

A timing controller includes a pipelined delay chain configured to process commands and control signals associated with the commands between a first device and a plurality of second devices having different timing requirements. The pipelined delay chain includes a cascaded arrangement of a primary delay chain, at least one secondary delay chain and a plurality of control signal sequence generators responsive to signals generated by the at least one secondary delay chain. The primary delay chain may include a plurality of serially-linked registers configured to support a pipelining of the commands and a stack configured to support operations to push and pop the control signals associated with the commands to and from the stack.

Timing controllers having partitioned pipelined delay chains therein

A multiple time domain synchronizer includes a data pipeline containing a plurality of serially-connected delay elements therein. A latency selection circuit is provided, which has a plurality of inputs electrically coupled to outputs of a corresponding plurality of delay elements in the data pipeline. The latency selection circuit is configured to pass a data pipeline signal from an output of a selected one of the plurality of delay elements in response to a latency control signal. A synchronization circuit is provided, which is electrically coupled to an output of the latency selection circuit. This synchronization circuit, which includes first and second unequal timing paths therein, is responsive to a clock that synchronizes capture of the data pipeline signal selected by the latency selection circuit and a destination code that selects one of the first and second unequal timing paths to be traversed by the captured data pipeline signal as active.

Multiple time domain synchronizer circuits

A packet switch includes an arbiter that generates an availability signal indicating whether one or more pseudo-ports are available for receiving data. Each pseudo-port identifies one or more output ports of the packet switch. An input port of the packet switch receives data of a data packet, generates a grant request identifying a pseudo-port, and issues the grant request to a grant request filter. The grant request filter determines based on the availability signal whether the grant request is serviceable by the packet switch. If the grant request is a serviceable grant request, the grant request filter issues the grant request to the arbiter. The arbiter can select the serviceable grant request and issue a grant to the input port. The data of the data packet can then be routed from the input port to each output port identified by the pseudo-port.

System and method for arbitration using availability signals

An arbiter generates an availability signal indicating whether pseudo-ports are available for receiving data. Each pseudo-port identifies one or more output ports of a packet switch. The availability signal also indicates whether each pseudo-port has a hold. A hold on a pseudo-port indicates that the pseudo-port is being held for an input port of the packet switch. Although the packet switch may complete routing of a data packet in progress to an output port of the pseudo-port that has the hold, the packet switch will not initiate routing of a data packet to an output port of the pseudo-port until each output port of the pseudo-port is available. When all the output ports of the pseudo-port are available, the packet switch can route data of a data packet from the input port for which the pseudo-port is being held to each output port of the pseudo-port.

System and method for arbitration of multicast data packets using holds

A switch includes an arbiter that receives a plurality of requests from N input ports, and determines N round robin arbitration option winners by performing N round robin arbitration options on the requests, each of the N round robin arbitration options performed assuming that a different one of the N input ports was a previous round robin arbitration winner. After the actual previous round robin arbitration winner is identified, a current round robin arbitration winner from among the N round robin arbitration option winners is determined by selecting the round robin arbitration option winner in which the assumed previous round robin arbitration winner is the actual previous round robin arbitration winner.

System and method for round robin arbitration

A packet switch arbitration system and method for arbitration in a packet switch. In one aspect, a method of issuing grants to an ingress port is disclosed in which a first grant request and burst signal are activated at an ingress port having more than one word available for transfer through the switch. A first grant is issued to the ingress port on a first interval. A subsequent grant is issued to the ingress port on a subsequent interval, where the subsequent grant is issued before the ingress port has validated the first grant request.

System and method for arbitration in a packet switch

An integrated circuit chip includes a plurality of independent FIFO memory devices that are each configured to support all four combinations of DDR and SDR write modes and DDR and SDR read modes and collectively configured to support all four multiplexer, demultiplexer, broadcast and multi-Q operating modes. The multi-Q mode of operation supports write path queue switching that is free of write word fall-through and read path queue switching that is free of read word fall-through. The multi-Q mode also supports write path queue switching on every write cycle in both SDR and DDR write modes and independent read path queue switching on every read cycle in both SDR and DDR read modes.

Multi-FIFO integrated circuit devices that support multi-queue operating modes with enhanced write path and read path queue switching

Integrated circuit memory devices support write and read burst modes of operation with uniformly short interconnect paths that provide high-speed memory access timing characteristics. These memory devices include a semiconductor chip having a memory core therein and at least N bond pads thereon. The memory core is configured to support a xN burst-M write mode of operation at QDR and/or DDR rates, where N is greater than four and M is greater than one. The memory core is further configured to support one-to-one mapping between burst-M write data received at each of the N bond pads and corresponding ones of N memory blocks in the memory core during the xN burst-M write mode of operation.

Multi-bank integrated circuit memory devices having high-speed memory access timing

An integrated circuit chip includes a plurality of independent FIFO memory devices that are each configured to support all four combinations of DDR and SDR write modes and DDR and SDR read modes and collectively configured to support all four multiplexer, demultiplexer, broadcast and multi-Q operating modes.

Integrated DDR/SDR flow control managers that support multiple queues and MUX, DEMUX and broadcast operating modes

An integrated circuit memory device includes a memory, a read control circuit operatively associated with the memory and configured to produce data from the memory responsive to an externally-applied input clock signal, and an output latch configured to transfer data at an input thereof to an output pad of the memory device responsive to an externally-applied output clock signal. The device further includes a clock domain alignment circuit configured to receive the data produced by the memory and to responsively provide the data at the input of the output latch based on relative timing of the input clock signal and the output clock signal.

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Suwanee, GA, United States of America

David Stuart Gibson