3com Corporation

David Stoner

Carl John Lindeborg

James Scott Hiscock

Norm Magnan

A switch of a computer network with a plurality of dual speed Ethernet client ports and at least one high speed Ethernet uplink port. The combined data rate of the Ethernet dual speed client ports has a maximum value which is higher than the data rate of the Ethernet uplink port. The Bandwidth Control limits the number of enabled Ethernet client ports so that the combined data rate of the enabled client ports substantially equals, or slights exceeds the data rate of the uplink port. In this way the speed and amount of switch memory can be minimized in the switch itself and the memory burden is divided among the clients. The dividing of the memory burden greatly reduces the worst case scenario and allows each client to individually chose the speed and amount of memory based on its own cost/benefit situation.

Method and apparatus for bandwidth control in an over subscribed

A LAN to ATM switch module includes a memory with an ATM port, a LAN port and a processor port. Each of port separately reading and writing information to/from the memory. An ATM interface is included for reading information from the ATM port and converting the information into an ATM format. The ATM interface also converts ATM format information to be delivered to the ATM port and written to the memory. A LAN interface reads information from the LAN port and converts the information into LAN format. The LAN interface also converts LAN information from a LAN packet channel bus to the LAN port, to be written to the memory. The switch module also includes a processor for reading information in the memory through the processor port. The processor determines the processing need for the information, the processor modifies the information in the memory according to the processing needed by writing to the memory through the processor port and controlling the ATM and LAN interfaces according to the processing needed.

LAN to ATM backbone switch module

A multiport or multiported memory device is provided. A first user and at least a second user are provided. A multilevel memory arbitration system is implemented which establishes arbitration cycles wherein the high priority user is granted priority as to access either during each arbitration cycle or during a greater number of arbitration cycles. A source burst limiter is provided associated with the high priority user. The source burst limiter monitors access of the high priority user to the multiport memory and limits such access based on a comparison of access attributes to some access attribute threshold.

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Sudbury, MA, United States of America

David Stoner