Mediatek Singapore Pte. Ltd.

David Stephen Ivory

Bernard Mark Tenbroek

A system is described that comprises: a master device and a slave device. The slave device comprises: a first die comprising an interface comprising a decoder configured to support a MIPI&#x2122; RFFE slave protocol; at least one second die comprising a simplified address decoder, operably coupled to the first die; and a shared control bus that is configured to support at least a clock signal and a data signal shared between the master device and the at least one second die on the slave device. The interface of the first die is configured to generate at least one circuit enable signal, routed to the at least one second die. The simplified address decoder is configured to process the clock signal and the data signal in response to the at least one circuit enable signal. In this manner, by partitioning the protocol handling to a protocol decoder in a first die, and one or more second die that support a simplified address decoder, the first die is able to individually select the die to receive a data frame by generating and routing the enable signal.

System comprising a master device and a slave device having multiple integrated circuit die, wireless communication unit and method therefor

An integrated circuit device includes at least a functional module arranged to receive a reference clock signal; a gating component configurable to perform gating of the reference clock signal; and a synchronization module. The synchronization module includes a trigger component arranged to receive a request for the functional module, the request being asynchronous with the reference clock signal, and to set an enable signal for the functional module in response to receiving the request therefor; and a synchronization component arranged to receive the enable signal, and in response to the enable signal being set to: configure the gating component to un-gate the reference clock signal; and synchronize an initial clock cycle of the reference clock signal received by the functional module following the reference clock signal being un-gated.

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Cambridge, United Kingdom

David Stephen Ivory