Hewlett-packard Development Company, L.p.

David Soper

Gary Belgrave Gostin

Ken Gary Pomaranski

Andrew Christopher Walton

John A Nerl

Roy M Zeighami

John M Wastlick

Brian Matthew Johnson

A method for controlling application of an erasure mode of an error correction code (ECC) algorithm in a memory subsystem includes detecting errors in cache lines retrieved from the memory subsystem using the ECC algorithm. The method also analyzes the errors to detect a repeated bit pattern of data corruption within the cache lines, correlates the detected repeated bit pattern of data corruption to one of a plurality of domains of the memory subsystem, and applies the ECC algorithm to erase bits associated with the detected repeated bit pattern from cache lines retrieved from the correlated domain of the memory subsystem.

System and method for controlling application of an error correction code (ECC) algorithm in a memory subsystem

A system utilizing an erasure mode in an error correction code algorithm is described that includes non-volatile memory storing a page deallocation table. A memory controller stores and retrieves data from a memory subsystem, and uses an error correction code algorithm to correct data corruption in retrieved data. An error analysis algorithm executed in a processor records instances of data corruption in the page deallocation tables and deallocates memory regions associated with multiple occurrences of data corruption at single bit locations. The error analysis algorithm further causes the memory controller to apply an erasure mode of the error correction code algorithm upon detection of a repeated pattern of data corruption across different addresses of the memory subsystem, and removes entries in the page deallocation table that correspond to data corruption addressed by application of the erasure mode.

System and method for applying error correction code (ECC) erasure mode and clearing recorded information from a page deallocation table

In one embodiment, a computer readable medium comprises code for recording occurrences of data corruption in data retrieved from a memory subsystem, code for determining whether bit locations within the memory subsystem are associated with multiple occurrences of data corruption, code for deallocating, in response to the code for determining, memory regions containing bit locations associated with multiple occurrences of data corruption, code for analyzing patterns of data corruption repeated across multiple addresses of the memory subsystem, and code for controlling application of an error correction code (ECC) algorithm by the memory subsystem to erase bits associated with a repeated bit pattern, detected by the code for analyzing, from data retrieved from the memory subsystem.

One embodiment is a method of dynamically adjusting a rate at which a dynamic random access memory ('DRAM') module is refreshed in a computer system. The method comprises monitoring a plurality of system conditions; detecting a change in at least one of the monitored system conditions; responsive to the detection, determining an optimum refresh rate for a current state of the computer system; and setting the refresh rate to the determined optimum refresh rate.

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Murphy, TX, United States of America

David Soper