Agere Systems Inc.

Intel Corporation

Lsi Corporation

Hewlett-packard Development Company, L.p.

Lucent Technologies Inc.

David Sonnier

Balakrishnan Sundararaman

David B Kramer

William G Burroughs

David Allen Brown

Shashank Nemawarkar

Gage Eads

Niall D McDonnell

Leslie Zsohar

Narender R Vangati

Shailendra Aulakh

Christopher E Koob

Hanan Z Moller

Stephen T Palermo

Shrikant M Shah

Bruce Richardson

Joseph R Hasting

Victor A Bennett

Abhishek Khade

Sean W McGee

Abhirupa Layek

Sarita Maini

Bradley Chaddick

Tsung-Yuan Charles Tai

Ren Wang

Andrew J Herdrich

Debra Bernstein

Jr-Shian Tsai

Stephen R Van Doren

Edwin Verplanke

Rahul R Shah

Hugh Wilkinson

Deepak Mital

Yipeng Wang

Andrew Cunningham

James T Clee

Jerry Pirog

Charles Edward Peet

Mrittika Ganguli

Jonathan Kenny

Te Khac Ma

David E Clune

Stephen Miller

Allen Vestal

Jamison D Whitesell

An Yan

Bradley A Burres

Namakkal N Venkatesan

Jian-Guo Chen

Robert J Munoz

Chris Randall Stone

Shannon E Lawson

Randy L Findley

Gary D Thompson

Robert W Horst

Asif Khan

Rahul C Shah

William J Watson

Chetan Hiremath

Joseph A Manzella

Steven J Pollock

Deepak Kataria

Ambalavanar Arulambalam

James Thomas Kirk

Michael R Betker

Seong-Hwan Kim

Christopher W Hamilton

James L Archibald

Ali A Poursepanj

Mark Benjamin Simkins

Milan Zoranovic

John Mangan

Walter A Roper

Rajarshi Bhattacharya

Nilesh S Vora

Rachel Flood

Michael W Hathaway

Niall Mcdonnell

Juergen Beck

Kevin S Grant

Robert B Mizell

Praveen Mosur

Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

Dynamic load balancing for multi-core computing environments

Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.

Hardware queue scheduling for multi-core computing environments

Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache ('LLC'), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

Multi-core communication acceleration using hardware queue device

Technologies for a distributed hardware queue manager include a compute device having a processor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

Technologies for a distributed hardware queue manager

Described embodiments provide for storing data in a local cache of one of a plurality of processing modules of a network processor. A control processing module determines presence of data stored in its local cache while concurrently sending a request to read the data from a shared memory and from one or more local caches corresponding to other of the plurality of processing modules. Each of the plurality of processing modules responds whether the data is located in one or more corresponding local caches. The control processing module determines, based on the responses, presence of the data in the local caches corresponding to the other processing modules. If the data is present in one of the local caches corresponding to one of the other processing modules, the control processing module reads the data from the local cache containing the data and cancels the read request to the shared memory.

Data caching in a network communications processor architecture

Described embodiments provide a method of controlling processing flow in a network processor having one or more processing modules. A given one of the processing modules loads a script into a compute engine. The script includes instructions for the compute engine. The given one of the processing modules loads a register file into the compute engine. The register file includes operands for the instructions of the loaded script. A tracking vector of the compute engine is initialized to a default value, and the compute engine executes the instructions of the loaded script based on the operands of the loaded register file. The compute engine updates corresponding portions of the register file with updated data corresponding to the executed script. The tracking vector tracks the updated portions of the register file. The compute engine provides the tracking vector and the updated register file to the given one of the processing modules.

Tracking written addresses of a shared memory of a multi-core processor

Described embodiments provide a method of coherently storing data in a network processor having a plurality of processing modules and a shared memory. A control processor sends an atomic update request to a configuration controller. The atomic update request corresponds to data stored in the shared memory, the data also stored in a local pipeline cache corresponding to a client processing module. The configuration controller sends the atomic update request to the client processing modules. Each client processing module determines presence of an active access operation of a cache line in the local cache corresponding to the data of the atomic update request. If the active access operation of the cache line is absent, the client processing module writes the cache line from the local cache to shared memory, clears a valid indicator corresponding to the cache line and updates the data corresponding to the atomic update request.

Described embodiments provide for dynamically controlling a scheduling rate of each node in a scheduling hierarchy of a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. A traffic manager enqueues received tasks in a queue of the scheduling hierarchy associated with a data flow. The queue has a parent scheduler at each level of the hierarchy up to the root scheduler. The traffic manager maintains one or more scheduling data structures for each node in the scheduling hierarchy. If the traffic manager receives a rate reduction request corresponding to a given node of the scheduling hierarchy, the traffic manager updates one or more indicators in the scheduling data structure corresponding to the given node and removes the given node from the scheduling hierarchy, thereby reducing the scheduling rate of the node.

Dynamic updating of scheduling hierarchy in a traffic manager of a network processor

A network-based apparatus for imposing a minimum transmit latency on data packets of a prescribed data type on a network includes at least one processor. The processor is operative: (i) to receive a data packet of the prescribed data type; (ii) to determine an elapsed time since an arrival of the received data packet at the apparatus; (iii) when the elapsed time is equal to or greater than the minimum transmit latency, to transmit the data packet; and (iv) when the elapsed time is less than the minimum transmit latency, to wait an amount of time at least equal to a difference between the elapsed time and the minimum transmit latency and then to transmit the data packet. The apparatus further includes memory coupled to the processor, the memory being configurable for storing data utilized by the processor.

Network based data traffic detection and control

Described embodiments provide a system having a plurality of processor cores and common memory in direct communication with the cores. A source processing core communicates with a task destination core by generating a task message for the task destination core. The task source core transmits the task message directly to a receiving processing core adjacent to the task source core. If the receiving processing core is not the task destination core, the receiving processing core passes the task message unchanged to a processing core adjacent the receiving processing core. If the receiving processing core is the task destination core, the task destination core processes the message.

Network communications processor architecture

Described embodiments provide a system having at least two network processors that each have a plurality of processing modules. The processing modules process a packet in a task pipeline by transmitting task messages to other processing modules on a task ring, the task messages related to desired processing of the packet. A series of tasks within a network processor may result in no processing or reduced processing for certain processing modules creating a virtual pipeline depending on the packet received by the network processor. At least two of the network processors communicate tasks. This communication allows ter the extension of the virtual pipeline of or IC network processor to at least two network processors.

Sharing of internal pipeline resources of a network processor with external devices

Described embodiments provide a method of processing packets of a network processor. One or more tasks are generated corresponding to received packets associated with one or more data flows. A traffic manager receives a task corresponding to a data flow, the task provided by a processing module of the network processor. The traffic manager determines whether the received task corresponds to a unicast data flow or a multicast data flow. If the received task corresponds to a multicast data flow, the traffic manager determines, based on identifiers corresponding to the task, an address of launch data stored in launch data tables in a shared memory, and reads the launch data. Based on the identifiers and the read launch data, two or more output tasks are generated corresponding to the multicast data flow, and the two or more output tasks are added at the tail end of a scheduling queue.

Multicasting traffic manager in a network communications processor architecture

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Austin, TX, United States of America

David Sonnier