Cadence Design Systems, Inc.

David Sliwinski

Joseph Michael Swenton

Thomas Webster Bartenstein

Richard Schoonover

Systems, methods, and computer readable media storing instructions for such methods relate to generating test vectors that can be used for exercising a particular area of interest in an integrated circuit. The test vectors generally include a non-overlapping repeating and/or predictable sequence of care bits (a care bit pattern) that can be used by a tester to cause the exercise of the area and collect emissions caused by exercising the area. Such emissions can be used for analysis and debugging of the circuit and/or a portion of it. Aspects can include providing a synchronization signal that can be used by a tester to allow sensor activation at appropriate times.

System to control insertion of care-bits in an IC test vector improved optical probing

Method and article of manufacture to generate IC test vector for synchronized physical probing

A system and method for isolating defects in scan chains by performing diagnostics fault simulation on chosen faults that are consistent with the nature of a scan chain defect, while keeping information about predictable failures. The effects of defects at specific locations on the scan chain are modeled by compositing the effects of a subset of the faults for each defect. Each composite, which models a specific scan chain defect, is evaluated in terms of how well it predicts the failures measured at a tester, and assigned a score based on that evaluation. The composite with the highest score identifies the modeled defect which is the closest to predicting the results measured at the tester, and therefore the location on the scan chain that has the highest probability of containing the actual defect.

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Vestal, NY, United States of America

David Sliwinski