Juniper Networks, Inc.

David Skinner

Pradeep S Sindhu

Raymond Marcelino Manese Lim

Sreeram Veeragandham

Rami Rahim

Deepak Goel

David James Ofelt

John Keen

Jianhui Huang

Venkatasubramanian Swaminathan

Ravi K Damaraju

A system for writing data includes a memory, at least one memory controller and control logic. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a reply that includes an address where the data unit is stored. The control logic receives the reply and determines whether the address in the reply differs from an address included in replies associated with other memory controllers by a threshold amount. When this occurs, the control logic performs a corrective action to bring an address associated with the memory controller back within a defined range.

Centralized memory allocation with write pointer drift correction

An example computing device includes a prefix lookup module, and a Bloom filter that includes a set of queues. The prefix lookup module is configured to receive policy configuration information, examine a state of a queue of the set of queues, and determine whether to bypass the first Bloom filter based on the policy configuration information and the state of the queue. In one example, the prefix lookup module may be configured to, using the policy configuration information, determine to bypass the Bloom filter when the queue is full. In another example, the prefix lookup module may be configured to, using the policy configuration information, determine not to bypass the Bloom filter and send a lookup request to the Bloom filter upon determining that the queue is no longer full.

Dynamic bypass mechanism to alleviate bloom filter bank contention

An arbiter system may include a first arbiter, a second arbiter, and selection logic. The first arbiter may be configured to select a first data identifier from among a group of data identifiers that are associated with a first bandwidth. The second arbiter may be configured to select a second data identifier from among another group of data identifiers that are associated with a second bandwidth. The selection logic may be configured to periodically select the first data identifier and the second data identifier so that the first data identifier and the second data identifier are respectively selected in proportion to the first bandwidth and the second bandwidth.

Programmable systems and methods for weighted round robin arbitration

A centralized memory allocation system utilizes write pointer drift correction. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a reply that includes an address where the data unit is stored. The control logic receives the reply and determines whether the address in the reply differs from an address included in replies associated with other memory controllers by a given address range. When this occurs, the control logic performs a corrective action to bring an address associated with the memory controller back within a defined range.

Incrementing successive write operations to a plurality of memory devices

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Los Altos, CA, United States of America

David Skinner