Texas Instruments Corporation

David Shippy

Jerald G Leach

A VLIW microprocessor capable of executing two or more instructions having data dependency in a single cycle. The microprocessor includes an instruction fetch and decode unit, a register file, and a plurality of execution units communicating with the instruction fetch and decode unit and with the register file. At least two of the execution units are connected such that the output of a first one of the two execution units is connected to the input of a second one of the two execution units, such that the output of the first execution unit is available as an input to the second execution unit during said single cycle, and such that both execution units can execute in said single cycle. In an exemplary embodiment, the first execution unit is a shift left unit, and the second execution unit is a shift right unit. With this embodiment, a complete extract operation can be performed in a single cycle.

Execution unit chaining for single cycle extract instruction having one

An adder unit for a microprocessor, being capable, in response to a first control signal, of adding two full word data values, stored in a first storage location and in a second storage location, respectively, and being capable, in response to a second control signal, of adding in parallel four half word data values, a first half word data value and a second half word data value being stored in the first storage location at the low half and the high half thereof, respectively, and a third half word data value and a fourth half word data value being stored in the second storage location at the low half and the high half thereof, respectively. The adder unit includes a first half word adder, arranged so as to add the first half word and the third half word to provide a first sum output of the adder unit, and a first carry out signal. The adder unit also includes a second half word adder arranged so as to add the second half word and the fourth half word, with a carry-in of 0 to provide a second sum output. The adder unit also includes a third half word adder arranged so as to add the second half word and the fourth half word, with a carry-in of 1 to provide a third sum output. Finally, the adder unit includes logic responsive to the first and the second control signals such that when the first control signal is present and the first carry-out signal is a 0, the logic provides the second sum output as a second sum output of the adder, to be concatenated with the first sum output of the adder, but, when the first control signal is present and the first carry-out signal is a 1, the logic provides the third sum output as a second sum output of the adder, to be concatonated with the first sum output of the adder. On the othe hand, when the second control signal is present, the logic provides the second sum output as a second sum output of the adder.

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Bellaire, TX, United States of America

David Shippy