International Business Machines Corporation

David Shing-Ki Kung

Ruchir Puri

Ulrich Alfons Finkler

Anthony Correale, Jr

Minsik Cho

Zhigang Pan

Vladimir P Zolotov

Prabhakar Nandavar Kudva

Douglass T Lamb

Li Feng Zhang

Rajiv V Joshi

David James Hathaway

Wei Zhang

Mark Alan Lavin

Meikei Ieong

Jinjun Xiong

Lakshmi Narasimha Reddy

Kathryn Wilder Guarini

Ibrahim M Elfadel

Leon Stok

David Wallach

Syed M Alam

Arifur Rahman

Rui Zhang

Siyuan Lu

Fook-Luen Heng

Puneet Gupta

Yang Zhang

Dung Tien Phan

Xiaodong Cui

Louise Helen Trevillyan

Anthony DeGroff Drumm

Nathaniel Douglas Hieter

Shiyu Chang

Marcus Oliver Freitag

Conrad M Albrecht

Mo Yu

Bhavna Agrawal

Daniel Lawrence Ostapko

William R Migatz

Paul M Campbell

Prabhakarn N Kudva

Jun-Dong Cho

Techniques that facilitate model support in deep learning are provided. In one example, a system includes a graphics processing unit and a central processing unit memory. The graphics processing unit processes data to train a deep neural network. The central processing unit memory stores a portion of the data to train the deep neural network. The graphics processing unit provides, during a forward pass process of the deep neural network that traverses through a set of layers for the deep neural network from a first layer of the set of layers to a last layer of the set of layers that provides a set of outputs for the deep neural network, input data for a layer from the set of layers for the deep neural network to the central processing unit memory.

Large model support in deep learning

Techniques for image processing and transformation are provided. A plurality of images and a plurality of maps are received, and a system of neural networks is trained based on the plurality of images and the plurality of maps. A first image is received, and a first map is generated by processing the first image using the system of neural networks.

Deep learning to correct map and image features

Various embodiments are provided for decentralized distributed deep learning by one or more processors in a computing system. Asynchronous distributed training of one or more machine learning models may be performed by generating a list of neighbor nodes for each node in a plurality of nodes and creating a first thread for continuous communication according to a weight management operation and a second thread for continuous computation of a gradient for each node. One or more variables are shared between the first thread and the second thread.

Decentralized distributed deep learning

Techniques regarding a zero-confidence adversarial attack are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an adversarial component that computes a perturbation that causes misclassification by a neural network classifier. The computer executable components can also comprise a restoration component that determines a normal vector to a constraint contour developed by the neural network classifier. Further, the computer executable components can comprise a projection component that determines a tangential vector to the constraint contour.

Margin based adversarial computer program

Embodiments for pipelining multi-directional reduction by one or more processors in a computing system. One or more reduce scatter operations and one or more all-gather operations may be assigned to each of a plurality of independent networks. The one or more reduce scatter operations and the one or more all-gather operations may be sequentially executed in each of the plurality of independent networks according to a serialized execution order and a defined time period.

Pipelining multi-directional reduction

A method for executing multi-directional reduction algorithms includes identifying a set of nodes, wherein a node includes at least one data element, creating a set of partitions including one or more data elements from at least two nodes, wherein the at least two nodes are arranged in a single direction with respect to the positioning of the set of nodes, executing a reduction algorithm on the data elements within the created set of partitions, creating an additional set of partitions including one or more data elements from at least two nodes, wherein the at least two nodes are arranged in a different direction with respect to the positioning of the set of nodes, executing a reduction algorithm on the data elements within the created additional set of partitions, and providing a set of reduced results corresponding to the at least one data element.

Multi-directional reduction in large scale deep-learning

Determining optimum values for Map Reduce parameters by identifying parameters that affect performance of a Map Reduce job, determining a relationship between each of the identified parameters and a maximization of resource utilization for a plurality of computing resources configured for executing the Map Reduce job, representing a workflow based upon supply-demand relationships among the plurality of computing resources, modeling an execution cost as a function of the plurality of identified parameters, formulating a non-linear programming problem to minimize the execution cost, reformulating the non-linear programming problem as a linear programming problem, and solving the linear programming problem to determine a combination of parameter values for the plurality of identified parameters that minimizes the execution cost for the Map Reduce job.

Performing automatic map reduce job optimization using a resource supply-demand based approach

In one embodiment, the invention is a method and apparatus for variation enabling statistical testing using deterministic multi-corner timing analysis. One embodiment of a method for obtaining statistical timing data for an integrated circuit chip includes obtaining deterministic multi-corner timing data for the integrated circuit chip and constructing the statistical timing data from the deterministic multi-corner timing data.

Enabling statistical testing using deterministic multi-corner timing analysis

A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Three dimensional integrated circuit and method of design

An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (V) supply and a high voltage island powered by a high voltage (V) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.

Multiple voltage integrated circuit and design method therefor

A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.

Single supply level converter

Three dimensional integrated circuit

A method, system and program product are described for generating a clock distribution network on an integrated circuit by determining an allowable placement region for each of a set of clock tree leaf elements in the integrated circuit. This allowable placement region is generated by determining and intersecting a set of sub-regions under different constraints, each of which identifies an area in which the clock tree leaf element is placed to satisfy the respective constraint. Constraints for which sub-regions are determined include timing constraints in the form of slacks and congestion constraints. After allowable placement regions have been determined, the clock tree leaf elements are clustered, and each clock tree leaf element is placed at a location within its allowable placement region which minimizes some cost function for that clustering.

Clock tree distribution generation by determining allowed placement regions for clocked elements

A method for performing timing closure on VLSI chips in a distributed environment is described. Abstracting the physical and timing resources of a chip and providing an asynchronous method of updating that abstraction allows multiple partitions of a chip to be optimized concurrently. A global view of physical and timing resources is supplied to local optimizations which are applied concurrently to achieve timing closure. Portions of the hierarchy are optimized in separate processes. Partitioning of the chip is performed along hierarchical lines, with each process owning a single partition in the hierarchy. The processes may be executed by a single computer, or spread across multiple computers in a local network. While optimizations performed by a single process are only applied to its given portion of the hierarchy, decisions are made in the context of the entire hierarchy. These optimizations include placement, synthesis, and routing. The present method can also be expanded to include other resources, such as routing resource, power supply current, power/thermal budget, substrate noise budget, and the like, all of which being able to be similarly abstracted and shared.

Method for performing timing closure on VLSI chips in a distributed environment

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Chappaqua, NY, United States of America

David Shing-Ki Kung