Samsung Electronics Co., Ltd.

Seoul National University

Leland Stanford Junior University

Sungkyunkwan University

Snur & Db Foundation

David Seo

Hyun-jong Chung

Jin-seong Heo

Seong-jun Park

Hyun-Jae Song

Kyung-Eun Byun

Myoung-jae Lee

Sun-ae Seo

Jae-ho Lee

Seong-ho Cho

In-kyeong Yoo

Chang-seung Lee

In-Kyeong Yoo

Sang-Wook Kim

Sung-Hun Lee

Ho-jung Kim

Seung-eon Ahn

Dong-Soo Lee

Sang-moon Lee

Jai-kwang Shin

Hyeon-jin Shin

Shigenobu Maeda

Mark Stephen Rodder

Yoon-Dong Park

Jae-Ho Lee

Young-soo Park

Jorge A Kittl

Sang Wook Kim

Seong-Ho Cho

Yun-sung Woo

Hee-jun Yang

Ji-hyun Hur

Hyung-cheol Shin

Jae-hong Lee

Moon-seung Yang

Young-jun Yun

Eui-chul Hwang

Young-Soo Joung

Young-Kwan Cha

Yung-hee Yvette Lee

Sae-ra Kang

Rwik Sengupta

Joo-ho Lee

Sang-Hun Jeon

Yong Sung Kim

Dong-seok Suh

Dong Wook Lee

Jae-Hwan Lee

Taeyong Kwon

Sun-Ae Seo

Young-hee Lee

Hye-Young Kim

Sang-Moon Lee

Mohammad Rakib Uddin

Young Jun Yun

Dong-Wook Lee

Seong Jun Park

Young Bae Kim

Chang Seung Lee

Hyeon-Jin Shin

Yung Hee Lee

Ji-Hyun Hur

Kota Oikawa

Kim Changhwa

Su-kang Bae

Myung-hee Jung

Seung-jae Baek

Eui-Chul Hwang

Hyun-Jong Chung

Jin-Seong Heo

Yun-Sung Woo

Seong-Jun Park

Hee-Jun Yang

Myoung-Jae Lee

Moon-Seung Yang

A method of manufacturing a graphene electronic device may include forming a metal compound layer and a catalyst layer on a substrate, the catalyst layer including a metal element in the metal compound layer, growing a graphene layer on the catalyst layer, and converting the catalyst layer into a portion of the metal compound layer.

Graphene electronic device and manufacturing method thereof

According to example embodiments, a graphene device includes a first electrode, a first insulation layer on the first electrode, an information storage layer on the first insulation layer, a second insulation layer on the information storage layer, a graphene layer on the second insulation layer, a third insulation layer on a first region of the graphene layer, a second electrode on the third insulation layer, and a third electrode on a second region of the graphene layer.

Graphene device and method of manufacturing the same

The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer.

Semiconductor device and method of fabricating the same

A method for forming a low parasitic capacitance contact to a source-drain structure of a fin field effect transistor device. In some embodiments the method includes etching a long trench down to the source-drain structure, the trench being sufficiently long to extend across all the of source-drain regions of the device. A conductive layer is formed on the source-drain structure, and the trench is filled with a first fill material. A second, narrower trench is opened along a portion of the length of the first trench, and filled with a second fill material. The first fill material may be conductive, and may form the contact. If the first fill material is not conductive, a third trench may be opened, in the portion of the first trench not filled with the second fill material, and filled with a conductive material, to form the contact.

Method for forming low parasitic capacitance source and drain contacts

A MOSFET may be formed with a strain-inducing mismatch of lattice constants that improves carrier mobility. In exemplary embodiments a MOSFET includes a strain-inducing lattice constant mismatch that is not undermined by a recessing step. In some embodiments a source/drain pattern is grown without a recessing step, thereby avoiding problems associated with a recessing step. Alternatively, a recessing process may be performed in a way that does not expose top surfaces of a strain-relaxed buffer layer. A MOSFET device layer, such as a strain-relaxed buffer layer or a device isolation layer, is unaffected by a recessing step and, as a result, strain may be applied to a channel region without jeopardizing subsequent formation steps.

Field effect transistor and method of fabricating the same

A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges.

Memory device using graphene as charge-trap layer and method of operating the same

Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element. A motion of an ionic species at the ionic species moving layer occurs according to a voltage applied to the gate electrode. A threshold voltage changes according to the motion of the ionic species. The nonvolatile memory transistor has a multi-level characteristic.

Nonvolatile memory transistor and device including the same

A graphene device and an electronic apparatus including the same are provided. According to example embodiments, the graphene device includes a transistor including a source, a gate, and a drain, an active layer through which carriers move, and a graphene layer between the gate and the active layer. The graphene layer may be configured to function both as an electrode of the active layer and a channel layer of the transistor.

Graphene device and electronic apparatus

Methods of fabricating graphene using an alloy catalyst may include forming an alloy catalyst layer including nickel on a substrate and forming a graphene layer by supplying hydrocarbon gas onto the alloy catalyst layer. The alloy catalyst layer may include nickel and at least one selected from the group consisting of copper, platinum, iron and gold. When the graphene is fabricated, a catalyst metal that reduces solubility of carbon in Ni may be used together with Ni in the alloy catalyst layer. An amount of carbon that is dissolved may be adjusted and a uniform graphene monolayer may be fabricated.

Methods of fabricating graphene using alloy catalyst

According to example embodiments, an electronic device includes: a semiconductor layer; a graphene directly contacting a desired (and/or alternatively predetermined) area of the semiconductor layer; and a metal layer on the graphene. The desired (and/or alternatively predetermined) area of the semiconductor layer include one of: a constant doping density, a doping density that is equal to or less than 10cm, and a depletion width of less than or equal to 3 nm.

Electronic device including graphene

A graphene device includes: a semiconductor substrate having a first region and a second region; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on the second region of the semiconductor substrate. The semiconductor substrate has a tunable Schottky barrier formed by junction of the graphene layer and the semiconductor substrate.

Graphene devices and methods of fabricating the same

A memory device includes a graphene switching device having a source electrode, a drain electrode and a gate electrode. The graphene switching device includes a Schottky barrier formed between the drain electrode and a channel in a direction from the source electrode toward the drain electrode. The memory device need not include additional storage element.

Memory devices including graphene switching devices

A switching device includes a semiconductor layer, a graphene layer, a gate insulation layer, and a gate formed in a three-dimensional stacking structure between a first electrode and a second electrode formed on a substrate.

Three-dimensional graphene switching device

A method of transferring graphene includes patterning an upper surface of a substrate to form at least one trench therein, providing a graphene layer on the substrate, the graphene layer including an adhesive liquid thereon, pressing the graphene layer with respect to the substrate, and removing the adhesive liquid by drying the substrate.

Method of transferring graphene using trench and substrate for receiving graphene

Growing community of inventors

Yongin-si, South Korea

David Seo