Infineon Technologies Ag

David Sellar

Burkhard Becker

Uwe Hildebrand

Peter Mahrla

Knut Just

Werner Hein

Michael Dolle

Hans-Georg Keller

David Jennings

Method for ascertaining an operating range for an integrated circuit which has a plurality of system components, in which a test routine is performed for testing at least one system component from the plurality of system components, where the at least one system component is not in operation and at least one other untested system component from the plurality of system components is ready for operation when the at least one system component is tested.

Integrated circuit and method for determining the operating range of an integrated circuit

Embodiments of the invention relate generally to an apparatus, to an embedded memory, to an address decoder, to a method of reading out data and to a method of configuring a memory. In an embodiment of the invention an apparatus is provided. The apparatus may include a plurality of read-only memory (ROM) cells and an address decoder to access a ROM cell of the plurality of ROM cells, the address decoder further being fuse-programmable to divert an access to the ROM cell to a different memory cell.

Apparatus, embedded memory, address decoder, method of reading out data and method of configuring a memory

The present invention provides a data processing apparatus having at least one dedicated data processing device () of a first type, a central data processing device () for controlling dedicated data processing devices (), at least one data transmission channel () for transmitting data between the data processing devices () and a data transmission device () for transmitting data between the data processing devices via the at least one data transmission channel () in a manner dependent on data transmission parameters, the data transmission parameters which are assigned to the at least one dedicated data processing device () of the first type being generated by the at least one dedicated data processing device () of the first type.

Data transmission device with a data transmission channel for the transmission of data between data processing devices

A timing device for generating and outputting a plurality of signal edges by changing signal statuses at predeterminable times. The timing device includes a cyclically addressable memory in which a plurality of time events are stored. Each time event is assigned a time value, which corresponds to a predetermined time, and a plurality of predetermined signal statuses. The timing device further includes a comparator, which compares the current count of a counter to the time value of a time event, which has just been acquired from memory. Given a match, the next time event is read from the memory. The timing device also includes an output device which outputs the predetermined signal statuses. With the timing device it is possible to freely program periodically recurring time indications by allocating memory accordingly.

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Munich, Germany

David Sellar