Infineon Technologies Ag

Cree Gmbh

Infineon Technologies Americas Corp.

David Seebacher

Peter Singerl

Christian Schuberth

Haedong Jang

Richard Wilson

Timothy Canning

Martin Mataln

Herwig Wappis

Franz Dielacher

Pantelis Sarais

Ji Zhao

Bayaner Arigong

Yannis Papananos

Nikolaos Alexiou

Andrea Del Chiaro

Alexander Komposch

Marc Tiebout

Frank Trang

Dmytro Cherniak

Fabio Padovan

Thomas Magesacher

Matteo Bassi

Rongguo Zhou

Tim Canning

Konstantinos Galanopoulos

Kostas Galanopoulos

In accordance with an embodiment, a method for operating a millimeter-wave power amplifier including an input transistor having an output node coupled to a load path of a cascode transistor includes: receiving a millimeter-wave transmit signal at a control node of the input transistor; amplifying the millimeter-wave transmit signal to form an output signal; providing the output signal to a load coupled to an output node of the cascode transistor; and adjusting a first DC bias current of the input transistor to form a substantially constant second DC bias current of the cascode transistor.

Millimeter-wave power amplifier

In sonic examples, a method includes pre-stressing a flange, heating the flange to a die-attach temperature, and attaching a die to the flange at the die-attach temperature using a die-attach material. In some examples, the flange includes a metal material, the die-attach temperature may be at least two hundred degrees Celsius, and the die-attach material may include solder and/or an adhesive. In some examples, the method includes cooling the semiconductor die and metal flange to a room temperature after attaching the semiconductor die to the metal flange at the die-attach temperature using a die-attach material.

Die-attach method to compensate for thermal expansion

Devices and methods for generating a bias voltage for a transceiver operating in time division multiplexing operation, and corresponding transceivers are provided. In this case, the bias voltage is controlled in guard intervals between transmission and reception of signals by the transceiver.

Method and device for providing a bias voltage in transceivers operating in time division multiplexing operation

A device includes at least one electrically conductive structure and at least one stripline. The stripline includes stripline sections that are connected to one another in a series connection between a first terminal and a second terminal. A first subset of the stripline sections is arranged on a first side of the conductive structure and a second subset of the stripline sections is arranged on a second side of the conductive structure. The device also includes at least one conductive connection between the first subset of the stripline sections and the second subset of the stripline sections, wherein the at least one conductive connection is isolated from the at least one electrically conductive structure.

Device having at least one subset of stripline sections on opposite sides of an electrically conductive structure and configured to have positive coupling

A circuit includes a first power transistor stage internally configured to function as a voltage-controlled current source, a second power transistor stage having an input impedance which varies as a function of input power and an interstage matching network coupling an output of the first power transistor stage to an input of the second power transistor stage. The interstage matching network is configured to provide impedance inversion between the input of the second power transistor stage and the output of the first power transistor stage. The impedance inversion provided by the interstage matching network transforms the first power transistor stage from functioning as a voltage-controlled current source to functioning as a voltage-controlled voltage source at the input of the second power transistor stage.

Interstage matching network

Devices including a transistor having a parasitic capacitance between a control terminal and a load terminal of a first type are provided. Furthermore, the devices include advantageously arranged inductances which are electromagnetically coupled to one another and are configured at least partly to compensate for an effect of the parasitic capacitance in a range around a resonant frequency.

Compensation device for transistors

A passive electrical component includes a substrate. A first metallization layer is formed on the substrate. A first dielectric layer is formed on the first metallization layer The first dielectric layer has a lower thermal conductivity than the substrate. A second metallization layer is formed on the first dielectric layer. An electrically conductive via provides an electrical connection between a first section of the first metallization layer and a second section of the second metallization layer. A thermally conductive via provides a thermally conductive path between the second section and the substrate. The thermally conductive via provides an open circuit termination to the second section of the second metallization layer.

Passive electrical component with thermal via

Method and device for providing a bias voltage in transceivers

A peaking amplifier is disclosed. The peaking amplifier includes a driver stage, a final stage, and an interstage matching network. The driver stage has a load impedance and is configured to generate a driver output based on an input signal. The final stage has a final stage input impedance and is configured to generate a peaking output based on the driver output. The interstage matching network is coupled to the driver stage and the final stage. The interstage matching network is configured to transform the final stage input impedance to the load impedance for the driver stage when the peaking amplifier is ON and to provide a short to an input of the final stage when the peaking amplifier is in an OFF state.

Devices and methods that facilitate power amplifier off state performance

A pulse width modulation system comprises an analog component and a digital component. The analog component operates to separate a local oscillator signal with different phase shifts and introduce an offset (i.e., a time delay) to analog signals being receive at an input with a tuning operation that fine tunes in the analog signals in the analog (continuous time) domain. The analog component comprises a plurality of analog delay lines that respectively process carrier signals having a different phase shifts. Digital delay lines convert the analog signals to digital square waves with the same time delay and at the same resolution as the analog output signal.

Mixed analog-digital pulse-width modulator

Techniques are provided for adapting a bias provided to a radio frequency (RF) power amplifier (PA), so as to achieve linear operation over a wide range of conditions. The techniques use open-loop temperature compensation based upon a sensed current during periods when the RF PA is active and inactive. A closed-loop control technique is enabled when the RF PA is inactive. The combined control techniques compensate for temperature variation as well as long-term drift of the semiconductor properties of the devices within the RF PA.

Adaptive biasing control for radio frequency power amplifiers

An amplifier circuit includes an RF input port, an RF output port, a reference potential port, and an RF amplifier having an input terminal and a first output terminal. An output impedance matching network electrically couples the first output terminal to the RF output port. A first inductor is electrically connected in series between the first output terminal and the RF output port, a first LC resonator is directly electrically connected between the first output terminal and the reference potential port, and a second LC resonator is directly electrically connected between the first output terminal and the reference potential port. The first LC resonator is configured to compensate for an output capacitance of the RF amplifier at a center frequency of the RF signal. The second LC resonator is configured to compensate for a second order harmonic of the RF signal.

Compact class-F chip and wire matching topology

A power amplifier includes an outphasing amplifier. The outphasing amplifier includes a first amplifier and a second amplifier, and is configured to provide a first amplified RF signal and a second amplified RF signal that is phase shifted from the first amplified RF signal. The power amplifier further includes an output circuit that is configured to combine RF power of the first and second amplified RF signals at a summing node. The output circuit includes a first branch connected between the first amplifier and a summing node and a second branch connected between the second amplifier and the summing node. The first and second branches are each configured to match an output impedance of the first and second amplifiers and to phase shift the first and second amplified RF signals for an outphasing operation using common reactive components for the match of the output impedance and the outphasing operation.

Compact chireix combiner and impedance matching circuit

An amplifier that is configured to amplify an RF signal includes a power combiner circuit. The power combiner circuit includes a first branch connected between a first RF input port and a summing node and a second branch connected between a second RF input port and the summing node. Each of the first and second branches includes an impedance inverter. The Chireix combiner is configured to present a Chireix load modulated impedance response to the first and second RF input ports. The power combiner circuit further includes compensation elements being configured to at least partially compensate for a reactance of the Chireix combiner circuit in a Doherty amplifier mode in which a signal is applied to the first RF input port and the second RF input port is electrically open.

Doherty-Chireix combined amplifier

A pulse width modulation (PWM) system comprises an analog component and a digital component. The analog component introduces an offset (i.e., a time delay) to analog signals being received at an input with a tuning operation that fine tunes in the analog signals in the analog (continuous time) domain. The analog component comprises an analog delay line comprising a plurality of analog delay components configured to introduce the time delay to the analog signals based on a model of a transmission line.

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Villach, Austria

David Seebacher