International Business Machines Corporation

Qualcomm Incorporated

David Scott Ray

Dwain Alan Hicks

Shih-Hsiung Stephen Tung

Brian David Barrick

Michael John Mayfield

Takeki Osanai

David James Shippy

Francis Patrick O'Connell

Dung Q Nguyen

Bryan J Lloyd

Kimberly Marie Fernsler

Benjamin W Stolt

James Allan Kahle

Barry Duane Williamson

Hung Qui Le

Sundeep Chadha

Thomas Philip Speier

Susan Elizabeth Eisen

Albert James Van Norstrand, Jr

Brian Stempel

Kurt Alan Feiste

Edward John Silha

Bruce Joseph Ronchetti

Kevin Arthur Chiarot

Joel M Tendler

Niket Choudhary

Alper Buyuktosunoglu

Pradip Bose

Michael Stephen Floyd

Harold Wade Cain, Iii

David Allen Hrusecky

Christopher Michael Abernathy

Eric Francis Robinson

Garrett M Drapala

Larry Edward Thatcher

Miles Robert Dooley

David Andrew Schroter

Joseph Gerald McDonald

Alexander K Spencer

Henry Stanley Warren, Jr

Gregory F Grohoski

A James Van Norstrand, Jr

Myhong Nguyenphu

Ravi Rajagopalan

Pritha Ghoshal

Patrick Eibl

Nikhil Narendradev Sharma

Kimberly Marie Fensler

Pei Chun Liu

An apparatus, method, and system for memory bandwidth aware data prefetching is presented. The method may comprise monitoring a number of request responses received in an interval at a current prefetch request generation rate, comparing the number of request responses received in the interval to at least a first threshold, and adjusting the current prefetch request generation rate to an updated prefetch request generation rate by selecting the updated prefetch request generation rate from a plurality of prefetch request generation rates, based on the comparison. The request responses may be NACK or RETRY responses. The method may further comprise either retaining a current prefetch request generation rate or selecting a maximum prefetch request generation rate as the updated prefetch request generation rate in response to an indication that prefetching is accurate.

Method, apparatus, and system for memory bandwidth aware data prefetching

A method, apparatus, and system for reducing pipeline stalls due to address translation misses is presented. An apparatus comprises a memory access instruction pipeline, a translation lookaside buffer coupled to the memory access instruction pipeline, and a TLB miss queue coupled to both the TLB and the memory access instruction pipeline. The TLB miss queue is configured to selectively store a first memory access instruction that has been removed from the memory access instruction pipeline as a result of the first memory access instruction missing in the TLB along with information associated with the first memory access instruction. The TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline associated with a return of an address translation related to the first memory access instruction.

Method, apparatus, and system for reducing pipeline stalls due to address translation misses

Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.

Speeding up younger store instruction execution after a sync instruction

In a processor core, high latency operations are tracked in entries of a data structure associated with an execution unit of the processor core. In the execution unit, execution of an instruction dependent on a high latency operation tracked by an entry of the data structure is speculatively finished prior to completion of the high latency operation. Speculatively finishing the instruction includes reporting an identifier of the entry to completion logic of the processor core and removing the instruction from an execution pipeline of the execution unit. The completion logic records dependence of the instruction on the high latency operation and commits execution results of the instruction to an architected state of the processor only after successful completion of the high latency operation.

Speculative finish of instruction execution in a processor core

A data processing system includes a processor, a unit that includes a multi-level cache, a prefetch system and a memory. The data processing system can operate in a first mode and a second mode. The prefetch system can change behavior in response to a desired power consumption policy set by an external agent or automatically via hardware based on on-chip power/performance thresholds.

Adaptive data prefetch

A load instruction that accesses data cache may be off natural alignment, which causes a cache line crossing to complete the access. The illustrative embodiments provide a mechanism for loading data across multiple cache lines without the need for an accumulation register or collection point for partial data access from a first cache line while waiting for a second cache line to be accessed. Because the accesses to separate cache lines are concatenated within the vector rename register without the need for an accumulator, an off-alignment load instruction is completely pipeline-able and flushable with no cleanup consequences.

Loading data to vector renamed register from across multiple cache lines

A method and apparatus are provided for detecting and handling an instruction flush in a microprocessor system. A flush mechanism is provided that is distributed across all of the execution units in a data processing system. The flush mechanism does not require a central collection point to re-distribute the flush signals to the execution units. Each unit generates a flush vector to all other execution units which is used to block register updates for the flushed instructions.

Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates

A pipeline processor has circuits to detect the presence of a register access instruction in an issue stage of the pipeline. A load-miss occurring at a later stage may cause the register access instruction to be marked with an associated bit. The register access instruction progresses down the pipeline and when the flush stage is reached, the processor checks the associated bit and flushes the register access instruction.

Method and apparatus for delaying a load miss flush until issuing the dependent instruction

The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a miss queue. And the load instruction is tagged as a local miss.

Load address dependency mechanism system and method in a high frequency, low power processor system

A method is disclosed for executing a load instruction. Address information of the load instruction is used to generate an address of needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache hit signal is generated. At least a portion of the address is used to search a queue for a previous load instruction specifying the same address. If a previous load instruction specifying the same address is found, the cache hit signal is ignored and the load instruction is stored in the queue. A load/store unit, and a processor implementing the method, are also described.

Systems for executing load instructions that achieve sequential load consistency

A method, an apparatus, and a computer program product are provided for detecting load/store dependency in a memory system by dynamically changing the address width for comparison. An incoming load/store operation must be compared to the operations in the pipeline and the queues to avoid address conflicts. Overall, the present invention introduces a cache hit or cache miss input into the load/store dependency logic. If the incoming load operation is a cache hit, then the quadword boundary address value is used for detection. If the incoming load operation is a cache miss, then the cacheline boundary address value is used for detection. This invention enhances the performance of LHS and LHR operations in a memory system.

Method of load/store dependencies detection with dynamically changing address length

Method and systems for executing load instructions that achieve sequential load consistency

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Georgetown, TX, United States of America

David Scott Ray