Qualcomm Incorporated

David Samuel Brackman

Chu-Cheow Lim

Sumeet Singh Sethi

Serafim S Loukas

An Mei Chen

Vijayalakshmi Rajasundaram Raveendran

Gordon Kent Walker

Thadi Manjunath Nagaraj

Fang Shi

Christopher John Bennett

Fang Liu

Scott T Swazey

Amnon Silberger

Serafim Loukas, Jr

Brian William Orr

Ramkumar Sampathkumar

Ammon Silberger

In one example, a device includes one or more processors configured to determine a set of optimization pass configuration data for code of a software program to be compiled, wherein the optimization pass configuration data defines a sequence of optimization passes for the software program during compilation, and execute the sequence of optimization passes on code for the software program based on the set of optimization pass configuration data.

Dynamic reconfigurable compiler

An apparatus includes a memory and a compiling processor configured to: generate, by at least one of a group consisting of a compiler and a runtime executing on the compiling processor, arguments for executing a compiled kernel, determine, by the at least one of the group executing on the compiling processor, whether a first memory reference to a first memory region and a second memory reference to a second memory region of the arguments refer to a same memory region, generate, by the at least one of the group, metadata associated with the first memory reference and the second memory reference based on the determination, wherein the metadata indicates a relationship between the first memory region and the second memory region. The at least one of the compiler and the runtime may recompile the kernel based on the metadata, and instruct a target processor to execute the recompiled kernel.

Memory reference metadata for compiler optimization

A temperature sensor may sense the temperature of a multi-core processor. In response to the temperature of the multi-core processor exceeding a temperature threshold for the multi-core processor, one or more busy processor cores of the multi-core processor may be power collapsed without reducing clock speed of the multi-core processor.

Accelerated thermal mitigation for multi-core processors

In one example, a device includes one or more processors configured to determine an allocated time for execution of an optimization pass for optimizing code for a software program, execute at least some instructions of the optimization pass on the code, and, in response to determining that an actual time for execution of the optimization pass has exceeded the allocated time for execution, preventing execution of subsequent instructions of the optimization pass.

Reducing excessive compilation times

In general, techniques are described for performing a form of inline dead code elimination. An apparatus comprising a storage unit and a processor may implement these techniques. The storage unit stores two source files and a destination file. The processor copies a first one of the source files to the destination file. This first source file includes a reference to a portion of a second one of the source files. The processor then evaluates the destination file to determine whether the portion of the second source file referenced in the first source file is used by the destination file. Based on the determination that the portion of the second source file referenced in the first source file is used by the destination file, the processor selectively copies the portion of the second source file to the destination file to generate an updated destination file.

Inline function linking

Techniques for video encoding and decoding channel switch frames (CSF) to enable acquisition and re/synchronization of the video stream while preserving compression efficiency is provided. Systems and methods to process multimedia data enabling channel switching are presented. The systems generate a CSF with one or more network adaptation layer (NAL) units as a random access point (RAP) frame. Back-to-back frames are transmitted which include the CSF and a non-RAP frame, each having the same frame ID number.

Systems and methods for channel switching

To set one or more events without intermediate scheduling of threads in a multi-threaded system, a scheduler is first rendered essentially ineffective. The events are then set, for example, by repeatedly calling a function to set a single event, once for each event to be set. The scheduler is then restored to its normal effectiveness. The scheduler may be rendered ineffective by artificially setting the priority of the current thread being processed to the highest possible priority level. This prevents the current thread from being preempted by another thread during the time that events are being set. After all events have been set, the priority of the current thread is restored to the original priority level, which then restores the scheduler to its normal effectiveness.

Growing community of inventors

San Diego, CA, United States of America

David Samuel Brackman