Apple Inc.

David S Zalatimo

Sandro Hermann Pintz

Marc Albrecht

Christopher P Tann

Chaohao Wang

Paolo Sacchetto

Fenghua Zheng

Guy Cote

Brijesh Tripathi

Hao Nan

Christopher Philip Alan Tann

Sean C Chang

Manev Luthra

Satish S Iyengar

Wei Hsin Yao

Jun Qi

Zhibing Ge

ByoungSuk Kim

Pierre-Yves Emelie

Chengrui Le

Tobias Jung

Shatam Agarwal

Lingyu Hong

Duane M Petrovich

Sachiko Oda

Hyunwoo Nho

Kingsuk Brahma

Jie Won Ryu

Wei Xiong

Nicolas P Bonnier

Yi Huang

Koorosh Aflatooni

Hyunsoo Kim

Taesung Kim

James E C Brown

Graeme M Williams

Teun R Baar

James E Brown

Yao Shi

Johan L Piper

Lei Zhao

Yaser Azizi

Li-Xuan Chuo

Jongyup Lim

Joseph P Manca

Jesse R Manders

An electronic device may include an electronic display having multiple display pixels that display an image based on dithered image data. The electronic device may also include image processing circuitry that generates the dithered image data based on input image data and a threshold gray level that is greater than one. Generating the dithered image data may include replacing each gray level of the input image data that is less than the threshold gray level with either a zero gray level or the threshold gray level according to a dither pattern.

Multi-least significant bit (LSB) dithering systems and methods

An electronic device may include a display having an array of pixels that receive data signals from multiple column driver integrated circuits. Each column driver integrated circuit may include gamma amplifiers that are used to set gamma references for driving the data signals. Each gamma reference can be set using first and second (redundant) gamma amplifiers in an alternating fashion to perform auto-zeroing. The auto-zeroing operation can be combined with a chopping operation to minimize amplifier offset across the different column driver integrated circuits. The auto-zeroing and/or the chopping function can be spatially alternated across the different rows in the array and temporally alternated across the different display frames.

Display column driver devices with offset cancellation

An electronic device may include an electronic display having multiple display pixels to display an image based on analog voltage signals. The electronic device may also include optical calibration circuitry to generate digital-to-analog converter (DAC) data based on image data associated with the image and dither circuitry to reduce a bit-depth of the DAC data, generating dithered DAC data. Additionally, the electronic device may include a gamma generator having one or more DACs to generate the analog voltage signals based on the dithered DAC data, which may instruct the gamma generator to generate the analog voltage signals indicative of the image data.

Dither enhancement of display gamma DAC systems and methods

Aspects of the subject technology relate to electronic device display circuitry and methods of operating the display. The display circuitry a panel driver interface that decodes digital display data, for each display frame, received from host circuitry of the electronic device. The digital display data includes error correction and detection information for frame and line configuration information distributed in a frame packet and multiple line packets for each display frame. The frame and line configuration information facilitates, efficient, low-error, digital control of various display operational features.

Panel driver interface systems and methods for electronic device displays

An electronic device may generate content that is to be displayed on a display. The display may have an array of liquid crystal display pixels for displaying image frames of the content. The image frames may be displayed with positive and negative polarities to help reduce charge accumulation effects. A charge accumulation tracker may analyze the image frames to determine when there is a risk of excess charge accumulation. The charge accumulation tracker may analyze information on gray levels, frame duration, and frame polarity. The charge accumulation tracker may compute a charge accumulation metric for entire image frames or may process subregions of each frame separately. When subregions are processed separately, each subregion may be individually monitored for a risk of excess charge accumulation.

Electronic device display with charge accumulation tracker

Aspects of the subject technology relate to electronic devices with displays. A display may include an array of display pixels and control circuitry for operating the display. The control circuitry may determine, based on pixel values for a row of display pixels, that a current in common supply voltage circuitry for the display pixels will exceed a threshold, if the row of display pixels is operated using the pixel values. The control circuitry may modify the pixel values for the row of display pixels to reduce the current in the common supply voltage circuitry and/or prevent the current in the common supply voltage circuitry from exceeding the threshold.

Current protection systems and methods for electronic device displays

An electronic device may be provided with a display. The display may include a backlight having an array of locally dimmable light sources. Control circuitry may provide control signals to the backlight to produce light at different brightness levels. When the brightness level is below a threshold, the control circuitry may use pulse-width-modulation control signals to control the light sources in the backlight. When the brightness level is above the brightness threshold, the control circuitry may use analog control signals to control the light sources in the backlight. The control circuitry may adjust the threshold to achieve different dimming ranges for different brightness settings. A low brightness setting, for example, may have a lower threshold and lower dimming range than a high brightness setting, which may help produce darker darks when the display operates in a low brightness setting.

Backlights with dynamic dimming ranges

A display may have a pixel array such as a liquid crystal pixel array. The pixel array may be illuminated by a backlight unit that includes an array of light-emitting diodes. A backlight brightness selection circuit may select brightness values for the light-emitting diodes. The backlight brightness selection circuit may select the brightness values based on image data, based on brightness values used in previous image frames, based on device information, and/or based on sensor information. The backlight brightness selection circuit may select the backlight brightness levels to mitigate visible artifacts such as flickering and halo. The backlight levels selected by the backlight brightness selection may be modified by a power consumption compensation circuit. The power consumption compensation circuit may estimate the amount of power consumption required to operate the backlight using the target brightness levels and may modify the target brightness levels to meet maximum power consumption requirements.

Display with adjustable direct-lit backlight units

Devices and methods for useful in providing localized synchronized and/or dynamic in-band internal gamma code adjustment per frame period are provided. By way of example, a display panel includes a data driver, which includes a first DAC configured to provide an internal gamma voltage signal to cause a first adjustment to an image data signal. The first adjustment is configured to selectively adjust the image data signal based at least in part on a refresh rate or a frame rate of the display panel. The data driver includes a second DAC coupled to the first DAC and configured to provide an external gamma voltage signal configured to provide a second adjustment to the image data signal, and an output buffer configured to supply the image data signal to pixels of the display panel, wherein the image data signal comprises the first adjustment and the second adjustment.

Internal gamma correction for electronic displays

Displays with adjustable direct-lit backlight units

Devices and methods for reducing or eliminating spatiotemporal dithering image artifacts are provided. By way of example, a method includes providing positive polarity and negative polarity data signals to a plurality of pixels of a display during a first frame period, in which the first frame period corresponds a first spatiotemporal rotation phase. The method includes providing the positive polarity signals and the negative polarity signals to the plurality of pixels of the display during a second frame period, in which the second frame period corresponds a second spatiotemporal rotation phase. A spatiotemporal rotation phase sequence provided to the display comprises the first spatiotemporal rotation phase and the second spatiotemporal rotation phase. One of the first spatiotemporal rotation phase and the second spatiotemporal rotation phase of the spatiotemporal rotation phase sequence is altered during the first frame period or the second time period.

Spatiotemporal dithering techniques for electronic displays

A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include gate driver integrated circuits. Each gate driver integrated circuit may have a shift register that supplies the gate line signals to the rows of pixels. The display driver circuitry supplies a clock signal to the gate driver integrated circuits. Each gate driver integrated circuit may have one or more clock trees that are selectively enable and disabled. Each gate driver integrated circuit may have a controller and a buffer that is controlled by a control signal from the controller. The buffer may be adjusted to supply or to not supply the clock signal to an associated clock tree in that gate driver integrated circuit.

Display driver circuitry with selectively enabled clock distribution

System and method for improving displayed image quality of an electronic display that displays a first image frame by applying a first voltage to a display pixel and a second image frame directly before the first image frame by applying a second voltage to the display pixel. A display pipeline is communicatively coupled to the electronic display and receives first image data corresponding with the first image frame, where the image data includes a first grayscale value corresponding with the display pixel. Additionally the display pipeline determines an inversion balancing grayscale offset based at least in part on the first grayscale value when polarity of the first voltage and polarity of the second voltage are the same and determines magnitude of the first voltage by applying the inversion balancing grayscale offset to the first grayscale value to reduce likelihood of a perceivable luminance spike when displaying the first image frame.

Inversion balancing compensation

Growing community of inventors

San Jose, CA, United States of America

David S Zalatimo