International Business Machines Corporation

David S Wolpert

Erwin Behnen

Leon Jacob Sigal

Robert Mahlon Averill, Iii

K Paul Muller

Michael S Gray

Takashi Ando

Reinaldo Ariel Vega

William Vincent Huott

Michael H Wood

Kevin W Kark

John Greg Massey

Timothy A Schell

David L Rude

Praneet Adusumilli

Cheng Chi

Christopher J Gonzalez

Matthew Thomas Guzowski

Ryan Michael Kruse

Mitchell R DeHond

Lawrence Alfred Clevenger

Terence B Hook

Kerry Bernstein

Alan P Wagstaff

Ruilong Xie

Chih-Chao Yang

Dureseti Chidambarrao

David James Hathaway

Marcel Mitran

Clarence Rosser Ogilvie

William J Rooney

Nicholas Anthony Lanzillo

Albert Manhee Chu

Paul Gerard Villarrubia

Steven Paul Ostrander

Alexander Joel Suess

Tao Li

Somnath Ghosh

Adam P Matheny

Matthew S Angyal

Daniel James Dechene

Basanth Jagannathan

Patrick D Watson

Atsushi Ogino

Tuhin Sinha

Richard Andre Wachnik

Joran S C Siu

Benjamin Neil Trombley

Michael Alexander Bowen

Laura R Darden

Gerald Strevig, Iii

Kyle Indukummar Giesen

Amanda Christine Venton

Richard Edward Serton

Brian G Veraa

Michael Romain

Bharat Biyani

Brian Veraa

James Leland

Samuel Sagan

Haard Kamlesh Mehta

Aspects of the invention include systems and methods configured to provide hierarchical circuit designs that makes use of effective metal density screens during hierarchical design rule checking (DRC) analysis. A non-limiting example computer-implemented method includes providing a first hierarchical level of a chip design. The first hierarchical level includes one or more internal shapes and at least one blockage shape having an internal structure defined at a second hierarchical level of the chip design. A tuple is assigned to the blockage shape. The tuple includes a metal layer identifier for the blockage shape, a minimum expected density for the blockage shape, and a maximum expected density for the blockage shape. The method includes determining whether a density violation exists in the first hierarchical level based in part on one or both of the minimum expected density for the blockage shape and the maximum expected density for the blockage shape.

Effective metal density screens for hierarchical design rule checking (DRC) analysis

Method and structures for shared (dual) sources for a single device in semiconductor devices such as very-large-scale integration (VLSI) devices. The shared-source improves or increases a current that passes through the device (e.g., to a drain region associated with the shared-source), which in turn increases a performance of the device. Example improvements may include a delay improvement of the device and associated logic paths and/or a power improvement for the device. The method includes operations for design improvements during a design process by implementing shared-sources in a semiconductor device design.

Cell optimization through source resistance improvement

An approach to forming a semiconductor device where the semiconductor device includes a first power rail that is connected to a decoupling capacitor by way of a first gate. The decoupling capacitor is also connected to a second gate. As such, the decoupling capacitor separates the first gate from the second gate. The decoupling capacitor may include a dielectric liner within a gate cut trench and a ferroelectric material over the dielectric liner. A second power rail may be connected to the decoupling capacitor by way of the second gate. The first gate and the second gate may be inline with respect thereto.

Decoupling capacitor inside gate cut trench

A semiconductor structure includes a first field-effect transistor having a first back side source/drain contact, a second back side source/drain contact, and a first power line and a first signal line each connected to the first back side source/drain contact and the second back side source/drain contact, respectively. The semiconductor structure further includes a second field-effect transistor vertically stacked above the first field-effect transistor. The second field-effect transistor having a first front side source/drain contact, a second front side source/drain contact, and a first power line and a first signal line each connected to the first front side source/drain contact and the second front side source/drain contact, respectively.

Transistors with dual power and signal lines

Method and apparatus for generating an updated power delivery network. Generating the power delivery network includes determining power characteristics for a power delivery network of a circuit design based on logic cells of the circuit design. The power delivery network includes power wires and power staples connecting pairs of the power wires to each other. Further a first one or more of the power staples is remove from the power delivery network based on the power characteristics. Signal wires for the logic cells are routed after removing the first one or more of the power staples. Routing the signal wires includes routing a first signal wire of the signal wires in a routing track corresponding to the first one or more of the power staples.

Generating a power delivery network based on the routing of signal wires within a circuit design

A capacitive memory cell includes an electrode, a tunneling barrier layer in direct contact with the electrode, a charge trapping layer in direct contact with the tunneling barrier layer, a ferroelectric layer in direct contact with the charge trapping layer, and another electrode in direct contact with the ferroelectric layer.

Negative capacitance for ferroelectric capacitive memory cell

Apparatus for mitigating latch-up within semiconductor devices. A semiconductor device includes a first conductor, a second conductor, and a first gate conductor. The first conductor extends in a first direction, receives a first power supply signal, and is connected to a first electrode. The second conductor extends in the first direction, receives a second power supply signal different from the first power supply signal, and is connected to a second electrode. The first conductor is offset from the second conductor in a second direction perpendicular to the first direction in a top-down view to mitigate formation of parasitic devices within the semiconductor device electrically connecting the first conductor with the second conductor. The first gate conductor is disposed adjacent to the first conductor and the second conductor, is disposed on the first electrode and the second electrode, and receives an input signal.

Semiconductor device design mitigating latch-up

Aspects of the invention include systems and methods configured to provide hierarchical circuit designs that makes use of a color decomposition of library cells having boundary-aware color selection. A non-limiting example computer-implemented method includes placing a plurality of shapes within a hierarchical level of a chip design. The plurality of shapes can include a top boundary shape, a bottom boundary shape, one or more center boundary shapes, and one or more internal shapes. A hierarchical hand-off region is constructed by pinning the top boundary shape to a first mask, pinning the bottom boundary shape to a second mask, and pinning the one or more center boundary shapes to a same mask. The same mask is selected from one of the first mask and the second mask.

Hierarchical color decomposition of library cells with boundary-aware color selection

An approach to forming a semiconductor device where the semiconductor device includes a first power rail with one or more vertically stacked contact vias connecting to the first power rail to a portion of a first de-coupling capacitor. The semiconductor device includes the first de-coupling capacitor in a first portion of a semiconductor substrate in a first gate cut trench.

Aspects of the invention include methods, systems, and computer program products for integrated circuit development using cross-hierarchy antenna condition verification. A method includes obtaining a design of a hierarchical macro distributed between multiple files for an integrated circuit and analyzing, by a design verification tool, a route between at least one child macro and at least one pin of the hierarchical macro as defined in the files. The method further includes determining, by the design verification tool, a plurality of connection characteristics of the at least one child macro and the at least one pin forming the route and calculating, by the design verification tool, an antenna condition for the route based on the connection characteristics. The design of the hierarchical macro is adjusted to remove a violation of an antenna rule based on determining that the antenna condition of the route violates the antenna rule.

Cross-hierarchy antenna condition verification

A semiconductor device is provided. The semiconductor device includes: a first conductive electrode; a first dielectric stack structure provided on the first conductive electrode; a second conductive electrode provided on the first dielectric stack structure; a second dielectric stack structure provided on the second conductive electrode; and a third conductive electrode provided on the first dielectric stack structure, wherein each of the first dielectric stack structure and the second dielectric stack structure include a first dielectric layer comprising a first material; a second ferroelectric dielectric layer comprising a second material and provided on the first dielectric layer, and a third dielectric layer comprising a third material and provided on the second ferroelectric dielectric layer.

Multilayer dielectric for metal-insulator-metal capacitor

Embodiments for power generation include defining a power tile within a power distribution network having a grid of power rails, the power tile having logic gates, and applying an initial power grid pattern from a plurality of power grid patterns for the power tile such that initial power grid pattern relates to timing characteristics of the logic gates of the power tile. The power grid patterns each have a different number of connectors connecting one power rail to another power rail in the grid of power rails. A subsequent power grid pattern is selected from the power grid patterns for the power tile such that the subsequent power grid pattern meets a threshold condition for the timing characteristics of the logic gates of the power tile. The timing characteristics for the logic gates are determined based on a voltage drop associated with the subsequent power grid pattern.

Region-based power grid generation through modification of an initial power grid based on timing analysis

A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.

Processor frequency improvement based on antenna optimization

A method can include obtaining characteristic data for a wafer. The characteristic data can correspond to the wafer in a processed state and can include a set of stress values of the wafer. The wafer can include a front side, a back side opposite the front side, and a set of regions. The set of stress values can include a first stress value corresponding to a first region. In the processed state, one or more front-side processes can be completed on the front side of the wafer. The method can include determining that the first stress value exceeds a stress threshold and generating a compensation map. The compensation map can identify one or more regions for forming one or more trenches. The method can include initiating, based on the compensation map, a formation of a first trench on the back side of the wafer in the first region.

Back-side wafer modification

Aspects of the invention include a computer-implemented method of chip design. The computer-implemented method of chip design include establishing an architecture with alternating rows of differently colored chip-level shapes. Cells are constrained to be rectangular with restricted widths. Constraint-observing parent and child cells are generated and respectively include boundaries with alternating rows of differently colored cell-level shapes for disposition in the architecture. The parent cell is positioned in the architecture such that the cell-level shapes thereof exhibit row and color alignment with the chip-level shapes. Child cells exhibiting uni-axial or multi-axial reflectivity are instantiated in the parent cell. A color solution is instantiated for each child cell in the parent cell such that cell-level shapes of the child cells exhibit row and color alignment with the cell-level shapes of the parent cell.

Hierarchical color decomposition of process layers with shape and orientation requirements

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Rochester, NY, United States of America

David S Wolpert