Apple Inc.

Google Inc.

Cambridge Display Technology Limited

David S Warren

Timothy R Paaske

Inna Levit

Jason Rupert Redgrave

Neeti Desai

Diarmuid P Ross

Asif Khan

Sukalpa Biswas

Erik P Machnicki

Euan Christopher Smith

Shane J Keil

Michael J Smith

Barry Thompson

Douglas C Lee

Stefan M Wurster

Weihua Mao

Richard Alan Page

Stephan Wurster

Richard Page

Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

System power management using communication bus protocols

An image processor is described. The image processor includes a storage circuit to store segments of input image data received in a raster scan format. The image processor further includes a reformatting circuit to convert the segments of input image data into a block image format. The image processor further includes a processor comprising a two-dimensional execution lane array and a two-dimensional shift register array. The two-dimensional shift register array is to store the input image data that has been formatted into the block image format. The execution lane array is to execute instructions that operate on the image data from the two-dimensional shift register array.

Image processor I/O unit

An image processor is described. The image processor includes a storage circuit to store segments of input image data received in a raster scan format from a camera. The image processor further includes a reformatting circuit to convert the segments of input image data into a block image format. The image processor further includes a processor comprising a two-dimensional execution lane array and a two-dimensional shift register array. The two-dimensional shift register array is to store the input image data that has been formatted into the block image format. The execution lane array is to execute instructions that operate on the image data from the two-dimensional shift register array.

In an embodiment, a peripheral interface controller may include an inline cryptographic engine which may encrypt data being sent over a peripheral interface and decrypt data received from the peripheral interface. The encryption may be transparent to the device connected to the peripheral interface that is receiving/supplying the data. In an embodiment, the peripheral interface controller is included in a system on a chip (SOC) that also includes a memory controller configured to couple to a memory. The memory may be mounted on the SOC in a chip-on-chip or package-on-package configuration. The unencrypted data may be stored in the memory for use by other parts of the SOC (e.g. processors, on-chip peripherals, etc.). The keys used for the encryption/decryption of data may remain within the SOC.

Embedded encryption/secure memory management unit for peripheral interface controller

A method of driving an electro-optic display comprising providing a current source, digitally modulating the current source and generating a modulated digital signal, and converting the modulated digital signal into an effective analog drive signal so that the display pixels receive an effective analog drive current, wherein the internal capacitance of the electro-optic display smooths the digitally modulated signal and generates the effective analog drive signal.

Method of driving an electro-optic display utilizing internal capacitance to smooth a digitally modulated signal

A clock divider may provide a lower speed clock to a logic block portion, but during reset, the clock divider may not operate properly, causing the logic block portion to be reset at a clock frequency greater than the frequency for which that logic was designed. However, an extended reset may be employed in which the clock divider is reset normally first before the logic block portion, allowing that logic to be reset according to the divided clock (e.g., rather than a higher speed clock). An asynchronous reset may also be employed in which one or more clock dividers first emerge from reset before being provided with a (synchronized) high speed clock signal, causing the clock dividers to be in phase with each other. This may enable communication between different areas of an IC that might not otherwise be in proper phase with each other.

Reset extender for divided clock domains

An apparatus includes a first unit and a second functional units operating in a master-slave configuration. The first and second functional units operate as a master and slave, respectively. The first functional unit conveys clock and framing signals to the second functional unit. The second functional unit includes a buffer and a multiplexer having inputs coupled to the buffer. Digital audio data may be prefetched into the buffer. When a controller of the second functional unit detects assertion of the framing signal, it may cause a change of state to a selection signal provided to the multiplexer. Responsive thereto, the multiplexer selects an input coupled to receive, from the buffer, a next frame of data to be transmitted. A first bit of the frame is transmitted to the first functional unit on the same clock cycle in which assertion of the framing signal was detected.

Slave mode transmit with zero delay for audio interface

A method and apparatus for scaling a DLL code for a slave DLL operating at a different frequency than a master DLL is disclosed. An apparatus includes a master DLL coupled to receive a first clock signal and a group of series-coupled slave DLLs coupled to receive a second clock signal. The master DLL may provide a specified fraction of a cycle of the first clock signal. Scaling circuitry coupled between the master DLL and the group of slave DLLs may determine a ratio of frequencies of the first clock signal to the second clock signal. Based on the ratio and a delay code from the first DLL, the scaling circuitry may generate an adjusted delay code received by the group of slave DLLs to set a delay for the second clock signal to the specified fraction.

Growing community of inventors

Campbell, CA, United States of America

David S Warren