Oasis Design, Inc.

Asahi Kasei Microsystems Co., Ltd.

David S Trager

David J Knapp

Tony Susanto

Larry L Harris

An apparatus is provided for automatically and dynamically adjusting a frequency division factor of a clock divider situated in the feedback loop of a phase-locked loop (PLL). The frequency division factor is modified based on changes in the input signal frequency forwarded to the PLL. If the input signal frequency increases, the decision circuit coupled to the input of the voltage controlled oscillator records that change as an encoded digital signal. That signal will accordingly modify the current frequency division factor dependent on current division factor as well as the current input signal frequency. The decision circuit can be modeled as an A/D converter, and the control unit placed between the decision circuit and the clock divider can be modeled as a state diagram. Each state of the state diagram is indicative of a frequency division factor, or a change in that division factor, wherein the coded digital signal indicates possible change from one state to another. By modifying the frequency division factor, the PLL can dynamically lock upon a changed input signal frequency without varying the clocking signal output from the PLL. Thus, the PLL can accommodate various input signal frequencies yet maintain a relatively fixed clocking signal to be forwarded as a timing reference to a digital processor.

Phase-locked loop which can automatically adjust to and lock upon a

A circuit is provided for controlling or regulating a phase-locked loop (PLL) output during times when the PLL is unlocked. Noise or corruption on the input signal of the PLL may cause the PLL output frequency to suddenly rise to match the input signal frequency. In many instances, the noise or corruption cannot be filtered by the low pass filter within the PLL. A detection circuit is coupled to receive the input signal, and discern times in which non-filterable noise occurs. The detection circuit may include a decoder which decodes, e.g., error correction coding within the input signal data stream to indicate possible instances in which the PLL will unlock. Once the detection circuit indicates an unlock condition and forwards an unlock selection signal to a multiplexer, the multiplexer chooses a frequency divided clocking signal rather than the PLL output clocking signal. The frequency divided clocking signal transitions at a rate acceptable to a digital processor, while the PLL output clocking signal during an unlock state is not acceptable. Thus, the digital processor can maintain its operating state during times when the PLL clocking signal exceeds the processor maximum operation frequency.

Phase-locked loop with protected output during instances when the

A digital filter is provided for achieving substantial attenuation of aliasing or imaging bands of a signal to be filtered. The digital filter employs a comb filter technique, wherein the comb filter can perform decimation or interpolation, depending upon its application. The comb filter is a multi-stage element, having more than one stage, and having an overall word length, W.sub.L, optimally reduced. The total number of terms within the cumulative set of stages is also optimally reduced. The comb decimation or interpolation filter architecture is therefore of minimum size if employed in hardware, or utilizes minimal operations if employed in software. A filter element within the comb decimation or interpolation filter includes a z-transform C.sub.K (Z) term. The filter element can be reduced to a simple z-transform 1+z.sup.-1 term if the stage of interest includes a decimate-by-two or interpolate-by-two rate change switch.

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Austin, TX, United States of America

David S Trager