Ventana Micro Systems Inc.

Ampere Computing LLC

David S Oliver

John G Favor

Michael N Michael

John Gregory Favor

Matthew Ashcraft

Alfred Yeung

Luca Ravezzi

Matthew W Ashcraft

A microprocessor includes a macro-op (MOP) cache (MOC) that holds MOC entries (MEs), including single-fetch block MEs (SF-MEs) and multi-fetch block MEs (MF-MEs), comprising MOPs decoded from architectural instructions. A prediction circuit generates fetch block (FBlk) start addresses (FBSAs) to make predictions of a sequence of FBlks fetched from an instruction cache and MEs fetched from the MOC. A back end detects that execution of a MOP of an MF-ME needs an abort and generates an abort request. A control circuit flushes all the MF-ME's MOPs and signals the prediction circuit to restart prediction at the MF-ME's FBSA. For each current FBSA of N current FBSAs used to make N predictions starting with the FBSA of the MF-ME, the prediction circuit ignores a hit on any MF-ME and instead, if the current FBSA hits on an SF-ME, predicts the SF-ME, and otherwise predicts a FBlk at the current FBSA.

Microprocessor that performs partial fallback abort processing of multi-fetch block macro-op cache entries

A microprocessor includes a macro-op (MOP) cache (MOC) having MOC entries (MEs) holding MOPs. An instruction fetch circuit fetches from the MOC the MOPS of an ME for execution, and a back-end detects that a MOP of the ME is causing a need for an abort type within a predetermined subset of abort types. A control circuit uses a location within the ME of the abort-causing MOP to determine an abort point that separates the ME into a former portion and a latter portion, flushes the MOPs of the latter portion of the ME, and allows the MOPs of the former portion of the ME to execute. After the flush of the MOPs of the latter portion of the ME, the microprocessor re-fetches and executes the MOPs of the latter portion of the ME but does not re-execute the MOPs of the former portion of the ME.

Microprocessor that performs mid-macro-op cache entry restart abort processing

A processor for mitigating side channel attacks includes units that perform fetch, decode, and execution of instructions and pipeline control logic. The processor performs speculative and out-of-order execution of the instructions. The units detect and notify the control unit of events that cause a change from a first translation context (TC) to a second TC. In response, the pipeline control logic prevents speculative execution of instructions that are dependent in their execution on the change to the second TC until all instructions that are dependent on the first TC have completed execution, which may involve stalling their dispatch until all first-TC-dependent instructions have at least completed execution, or by tagging them and dispatching them to execution schedulers but preventing them from starting execution until all first-TC-dependent instructions have at least completed execution. The processor may also in response prevent speculative instruction fetching and/or perform speculative instruction flushing.

Processor that prevents speculative execution across translation context change boundaries to mitigate side channel attacks

A microprocessor includes a decode unit that maps architectural instructions into micro-operations and dispatches them to a scheduler that issues them to execution units that execute them by reading source operands from a register file and writing execution results to the register file. An architectural instruction instructs the microprocessor to load a constant into an architectural destination register. The decode unit maps the architectural instruction into a load constant micro-operation (LCM) and writes the LCM constant directly to a register of the register file without dispatching the LCM to the scheduler, such that the LCM is not issued to the execution units. In the same clock cycle, the decode unit indicates the LCM constant is available for consumption, such that the LCM imposes zero execution latency on dependent micro-operations and dispatches to the scheduler micro-operations other than the LCM. The register file may include a decode unit-dedicated write port.

Microprocessor including a decode unit that performs pre-execution of load constant micro-operations

Various aspects provide for mitigating voltage droop associated with a microprocessor (e.g., by controlling a clock associated with the microprocessor). For example, a system can include a microprocessor and a controller. The microprocessor can receive a clock provided by a clock buffer. The controller can control frequency of the clock provided by the clock buffer based on a voltage associated with the microprocessor. In an aspect, the controller can reduce the frequency of the clock in response to a determination that the voltage satisfies a defined criterion. Additionally, the controller can incrementally increase the frequency of the clock in response to another determination that the voltage satisfies another defined criterion after satisfying the defined criterion.

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Providence, UT, United States of America

David S Oliver