3com Corporation

David S Miller

Kenneth J DeLong

Edward A Heiner, Jr

Lawrence Aaron Boxer

Brian Bisceglia

Flow of data units to an address resolution processor is controlled to inhibit multiple data units from a single multicast flow from being enqueued with the address resolution processor. In a switch having a plurality of Input/Output Application Specific Integrated Circuits (&ldquo;I/O ASICs&rdquo;) with a plurality of ports, no more than one data unit from each I/O ASIC is permitted to be enqueued with the address resolution processor at any point in time. A separate learn pending indicator may be defined for each I/O ASIC in the switch.

Learn pending frame throttle

A method and apparatus is disclosed for extending PHY addressing in a telecommunications device beyond the number of PHYS that may be directly addressed over a bidirectional serial management control bus using a management bus protocol employing a predetermined number of address bits for PHY addressing. A plurality of serial bidirectional management control buses are provided and plural PHYS are coupled to each of the buses. A control processor is employed in conjunction with control logic to select one of the plurality of management control buses as the active bus at any one time to permit communication between the processor and a selected PHY on the respective bus. State machines within the programmable array logic are employed to selectively enable buffers within the control logic to allow the processor to write information to a PHY on a selected control bus or alternatively, to allow the processor to read information from a PHY on a selected control bus. In the above described manner, any desired number of PHYS may be addressed by a single control processor within the telecommunications device. Additionally, a serial peripheral channel within the processor is employed to offload the processor from control bus management functions. The serial peripheral channel is loaded by the control processor and the channel manages the serial communication over the control bus. In this manner, the bandwidth of the processor is available for port management and statistics gathering functions.

Extended PHY addressing

A cache line index for an address cache entry is calculated by organizing an address such as a Media Access Control (&ldquo;MAC&rdquo;) address into a plurality of intermediate elements, barrel shifting the bits of at least one of the intermediate elements in accordance with predetermined criteria, and folding the intermediate address elements together with an exclusive-OR function. A Virtual Local Area Network (&ldquo;VLAN&rdquo;) index may also be included in cache line index calculation. The VLAN index enables segmentation of the cache into virtual tables. The tag portion of the cache entry includes a subset of the complete set of intermediate elements. The intermediate elements in the cache entry can be employed in conjunction with the cache line index to recover the original MAC address. Hence, the size of the tag portion of the address cache entry is reduced relative to the full MAC address without a reduction in the information content of the entry.

Hash equation for MAC addresses that supports cache entry tagging and virtual address tables

An arbiter circuit is employed to isolate a processor from a plurality of Input/Output Application Specific Integrated Circuits ('I/O ASICs'). The processor is coupled to the arbiter through a control bus, an address bus and a data bus. The arbiter is coupled to the I/O ASICs through an extension of the control bus and a combined address/data bus. The arbiter manages control of the control bus extension and address/data bus to enable contemporaneous transmission ('broadcast') of messages to the I/O ASICs, and enable the processor to access the I/O ASICs. Only one of the I/O ASICs is granted control of the control bus extension and address/data bus at any point in time. The processor may also be granted sole control of the control bus extension and address/data bus.

Growing community of inventors

Framingham, MA, United States of America

David S Miller