International Business Machines Corporation

Motorola Corporation

Globalfoundries Inc.

David S Levitan

Brian R Konigsburg

Mauricio J Serrano

Balaram Sinharoy

Richard James Eickemeyer

Sheldon Bernard Levenstein

Jose Eduardo Moreira

Albert James Van Norstrand, Jr

Lixin Zhang

Nicholas R Orzol

Brian William Thompto

Brian Robert Mestan

John Wesley Ward, Iii

Mehul N Patel

Tejas S Karkhanis

Wolfram M Sauer

Hung Qui Le

James Allan Kahle

Gregory William Alexander

John Stephen Muhich

Samuel Jonathan Thomas

Robert Alan Philhower

Chin-Cheng Kau

William John Starke

Giles R Frazier

Lee Evan Eisen

Richard William Doing

David Mui

John Edward Derrick

Aubrey Deene Ogden

Kevin Neal Magill

Jeffrey Richard Summers

Paul C Rossbach

Akash V Giri

Douglas R G Logan

Bruce Martin Fleischer

Steven Wayne White

Susan Elizabeth Eisen

Phillip G Williams

William Evan Speight

Kattamuri Ekanadham

Ronald Nick Kalla

William Elton Burky

Shashank Nemawarkar

Francis Patrick O'Connell

Adam R Talcott

Benjamin W Stolt

Naga P Gorti

Glenn Owen Kincaid

Donald E Waldecker

Il Park

Scott Bruce Frommer

Wolfram Sauer

Bryan Glen Hickerson

Ali A Poursepanj

Robert William Hay

Michael Normand Goulet

Douglas Robert Gordan Logan

Paul K-g Tu

Danny K Jain

A processor reads at least one instruction comprising at least one of a branch instruction and a non-branch instruction. In response to the branch instruction comprising a conditional branch instruction and set in dynamic mode, the processor dynamically predicts a branch path as taken or not taken. The processor, in response to the instruction fetch unit set in static mode for a conditional branch instruction and static branch prediction setting bits received with the conditional branch instruction specifying static branch prediction, statically sets the branch path as taken or not taken according to the static branch prediction setting bits received with the branch instruction. The processor selectively sets the operation of the processor temporarily from the dynamic mode to the static mode only in response to detecting a type of the at least one instruction matches a type of instruction qualifying to trigger static branch prediction.

Selectively supporting static branch prediction settings only in association with processor-designated types of instructions

Predicting indirect branch instructions may comprise predicting a target address for a fetched branch instruction. Accuracy of the target address may be tracked. The fetched branch instruction may be flagged as a problematic branch instruction based on the tracking. A pattern cache may be trained for predicting a more accurate target address for the fetched branch instruction, and the next time the fetched branch instruction is again fetched, a target address may be predicted from the pattern cache.

Predicting indirect branches using problem branch filtering and pattern cache

Operation of a multi-slice processor implementing a tagged geometric history length prediction unit and an effective address table aligned with an update table, where the multi-slice processor includes a plurality of execution slices. Operation of such a multi-slice processor includes: receiving, at an effective address table and at a TAGE update table, information for a branch instruction dispatched to an execution slice, wherein the effective address table and the TAGE update table are in alignment; responsive to the branch instruction being taken, updating the effective address table and the TAGE update table to indicate the branch instruction being taken; and updating, in dependence upon the alignment between the effective address table and the TAGE update table, the TAGE branch prediction unit with update information from both the effective address table and the TAGE update table.

Operation of a multi-slice processor implementing tagged geometric history length (TAGE) branch prediction

Instruction prefetching in a computer processor includes, upon a miss in an instruction cache for an instruction cache line: retrieving, for the instruction cache line, a prefetch prediction vector, the prefetch prediction vector representing one or more cache lines of a set of contiguous instruction cache lines following the instruction cache line to prefetch from backing memory; and prefetching, from backing memory into the instruction cache, the instruction cache lines indicated by the prefetch prediction vector.

Instruction prefetching in a computer processor using a prefetch prediction vector

A computer processor includes a branch prediction unit that includes a local branch predictor and a global branch predictor. Managing power consumption in such a computer processor includes, for each of a plurality of branch instructions: performing, by the local branch predictor, a local branch prediction; performing, by each of the global branch predictors, a global branch prediction; determining to utilize the local branch prediction over the global branch predictions as a branch prediction for the branch instruction; incrementing a value of a counter; determining whether the value of the counter exceeds a predetermined threshold; and if the value of the counter exceeds the predetermined threshold, powering down at least one of the global branch predictors and configuring the branch prediction unit to bypass the powered down global branch predictor for branch predictions of subsequent branch instructions.

Power management of branch predictors in a computer processor

Variable latency flush filtering including receiving a first flush instruction tag (ITAG) and a second flush ITAG, wherein the first flush ITAG and the second flush ITAG are instructions to invalidate internal operation results after an internal operation identified by the first flush ITAG and the second flush ITAG; determining that the second flush ITAG is before the first flush ITAG by comparing the first flush ITAG and the second flush ITAG; determining that the first flush ITAG requires adjustment; and delaying the flush to a subsequent cycle in response to determining that the second flush ITAG is before the first flush ITAG and determining that the first flush ITAG requires adjustment.

Variable latency flush filtering

Blocking instruction fetching in a computer processor, includes: receiving a non-branching instruction to be executed by the computer processor; determining whether executing the non-branching instruction will cause a flush; and responsive to determining that executing the non-branching instruction will cause a flush, disabling instruction fetching for the computer processor for a time, including recoding the instruction such that the recoded instruction will be interpreted by an instruction fetch unit as an unconditional branch instruction.

Blocking instruction fetching in a computer processor

Methods and apparatus for generating a mask vector for determining a processor instruction address using an instruction tag (ITAG) in a multi-slice processor including receiving a first ITAG value and an interrupt ITAG value; generating the mask vector divided into mask sections comprising a plurality of elements with unset flags; for each mask section: if the mask section comprises the first ITAG value, setting a flag of an element in the mask section corresponding to the first ITAG value; if the mask section comprises the interrupt ITAG value, setting a flag of an element in the mask section corresponding to the interrupt ITAG value; setting each flag of each element in the mask vector between the element in the mask vector corresponding to the first ITAG value and the element in the mask vector corresponding to the interrupt ITAG value; and providing the mask vector to an instruction fetch unit.

Generating a mask vector for determining a processor instruction address using an instruction tag in a multi-slice processor

Methods and apparatus for identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor including receiving, by an instruction fetch unit of the processor, the interrupt ITAG; retrieving an effective address table (EAT) row from an EAT, wherein the EAT row comprises a range of EAs and a first ITAG of a range of ITAGs; accessing a processor instruction vector comprising a plurality of elements, each element corresponding to one of a plurality of ITAGs; applying a mask to the processor instruction vector to obtain a portion of the processor instruction vector that begins with an element corresponding to the first ITAG and is defined by an element corresponding to the interrupt ITAG; calculating an EA offset; and identifying the EA for the interrupt ITAG using the EA offset and the range of EAs in the retrieved EAT row.

Identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor

A technique for operating a processor includes allocating an entry in a prefetch filter queue (PFQ) for a cache line address (CLA) in response to the CLA missing in an instruction cache. In response to the CLA subsequently hitting in the instruction cache, an associated prefetch value for the entry in the PFQ is updated. In response to the entry being aged-out of the PFQ, an entry in a backing array for the CLA and the associated prefetch value is allocated. In response to subsequently determining that prefetching is required for the CLA, the backing array is accessed to determine the associated prefetch value for the CLA. A cache line at the CLA and a number of sequential cache lines specified by the associated prefetch value in the backing array are then prefetched into the instruction cache.

Dynamic sequential instruction prefetching

A technique for operating a processor includes identifying a difficult branch instruction (branch) whose target address (target) has been mispredicted multiple times. Information about the branch (which includes a current target and a next target) is learned and stored in a data structure. In response to the branch executing subsequent to the storing, whether a branch target of the branch corresponds to the current target in the data structure is determined. In response to the branch target of the branch corresponding to the current target of the branch in the data structure, the next target of the branch that is associated with the current target of the branch in the data structure is determined. In response to detecting that a next instance of the branch has been fetched, the next target of the branch is utilized as the predicted target for execution of the next instance of the branch.

Techniques for predicting a target address of an indirect branch instruction

Branch prediction in a computer processor, includes: fetching an instruction, the instruction comprising an address, the address comprising a first portion of a global history vector and a global history vector pointer; performing a first branch prediction in dependence upon the first portion of the global history vector; retrieving, in dependence upon the global history vector pointer, from a rolling global history vector buffer, a second portion of the global history vector; and performing a second branch prediction in dependence upon a combination of the first portion and second portion of the global history vector.

Branch prediction in a computer processor

Methods and apparatus for managing an effective address table (EAT) in a multi-slice processor including receiving, from an instruction sequence unit, a next-to-complete instruction tag (ITAG); obtaining, from the EAT, a first ITAG from a tail-plus-one EAT row, wherein the EAT comprises a tail EAT row that precedes the tail-plus-one EAT row; determining, based on a comparison of the next-to-complete ITAG and the first ITAG, that the tail EAT row has completed; and retiring the tail EAT row based on the determination.

Managing an effective address table in a multi-slice processor

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Austin, TX, United States of America

David S Levitan