Intel Corporation

David S Bormann

Frank P Hart

Leslie E Cline

Chao-Hsin Chi

Dong Tieu

Edwin J Pole, Ii

Kirk Skeba

Siripong Sritanyarantana

Rudi Rughoonundon

A method and apparatus for facilitating direct access to a serial Advanced Technology Attachment (ATA) device by an autonomous subsystem in the absence of the main operating system (OS).

Method and apparatus facilitating direct access to a serial ATA device by an autonomous subsystem

A method and apparatus for facilitating direct access to a parallel Advanced Technology Attachment (ATA) device by an autonomous subsystem in the absence of the main operating system (OS).

Method and apparatus facilitating direct access to a parallel ATA device by an autonomous subsystem

A method and apparatus for facilitating direct access to computer resources by a peripheral device while the computer's CPU is in a sleeping state. A peripheral device having a circuit to detect the power management state of a central processor, a first interface to couple the device to the central processor if the circuit detects the first power management state, and a second interface to couple the device to a peripheral device if the circuit detects the second power management state.

Method and apparatus to directly access a peripheral device when central processor operations are suspended

Transmitting data on a serial data transmission path to reduce latency including reading only enough of a device address of a serial data word to determine if the serial data word is addressed to a first device having an address, wherein the serial data word is transmitted across a first link of a first serial data transmission path to the first device and passing the serial data word across a second link of the first serial data transmission path to a second device if the serial data word is not addressed to the first device.

Daisy chain latency reduction

A peripheral device having a circuit to detect the power management state of a central processor, a first interface to receive data, and a second interface to couple the peripheral device to the central processor. The peripheral device prevents data transfers that would cause the central processor to change from a second power management state to a first power management state if the central processor is in the second power management state.

Computer peripheral device that remains operable when central processor operations are suspended

Speculative memory commands are prepared for reduced latency. A system memory read request is sent for preparing a main memory read command and for performing a cache lookup. The main memory read command is prepared independent from the performance of the cache lookup.

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Sunnyvale, CA, United States of America

David S Bormann