Advanced Micro Devices Corporation

David S Bang

Zoran Krivokapic

Shekhar Pramanick

Takeshi Nogami

Guarionex Morales

Qi Xiang

Ming-Ren Lin

Witold P Maszara

Srinath Krishnan

Ming-Yin Hao

A test structure used to measure metal bottom coverage in semiconductor integrated circuits. The metal is deposited in etched trenches, vias and/or contacts created during the integrated circuit manufacturing process. A predetermined pattern of probe contacts are disposed about the semiconductor wafer. Metal deposited in the etched areas is heated to partially react with the underlying and surrounding undoped material. The remaining unreacted metal layer is then removed, and an electrical current is applied to the probe contacts. The resistance of the reacted portion of metal and undoped material is measured to determine metal bottom coverage. Some undoped material may also be removed to measure metal sidewall coverage. The predetermined pattern of probe contacts is preferably arranged in a Kelvin or Vander Paaw structure.

Test structure used to measure metal bottom coverage in trenches and vias/contacts and method for creating the test structure

A design for an MOS transistor deliberately uses depletion in a polysilicon gate electrode to improve circuit performance. Conventional transistor design seeks to minimize depletion in a polysilicon gate electrode to increase drive current. According to an embodiment of the present invention, appropriate levels of depletion in the gate electrode, larger than conventional levels, simultaneously provide desired drive current while minimizing circuit delay. According to another aspect, circuit performance is improved by adjusting doping levels in the channel region to maintain a threshold voltage at the same level as that which is achieved with minimum depletion in a polysilicon gate electrode. A method of fabricating an MOS device including a polysilicon gate electrode with increased depletion is also provided. A self-aligned doping process is used in which the polysilicon gate, the source region, and the drain region, are simultaneously implanted to dopant concentrations of between 1&times;10,and 5&times;10,atoms/cm,.

Method of improving MOS device performance by controlling degree of depletion in the gate electrode

A method of reducing intralevel capacitance in a damascene metalization process employs entrapped air gaps between metal lines. The method involves forming a metalization pattern using a damascene process which includes forming at least first and second metal regions separated by a dielectric region, forming an air gap at least partially within the dielectric region, and sealing the air gap to entrap the air gap between the first and second metal regions thereby reducing intralevel capacitance between the first and second metal regions.

Method of producing air gap for reducing intralayer capacitance in metal layers in damascene metalization process and product resulting therefrom

An integrated circuit and a method of forming an integrated circuit is described. The integrated circuit includes a silicon substrate, a dielectric stack formed on the silicon substrate, and conductive metal lines overlying the silicon substrate. A first layer of low-k dielectric material overlies the at least one conductive metal line, and a second layer of low-k dielectric material overlies the first layer of low-k dielectric material. The first layer of low-k dielectric material is electron beam (E-beam) cured and the second layer of low-k dielectric material is thermally cured.

Electron bean curing of low-k dielectrics in integrated circuits

Test structure used to measure metal bottom coverage in trenches and

An ultra-thin dielectric film is subject to a dynamic electrical bias. During a first phase, the ultra-thin dielectric film is under a high field bias generated by the application of a high voltage. The duration of the high electrical stress is dependent on the intrinsic properties of the ultra-thin dielectric material. In a second phase, the ultra-thin dielectric film is subjected to an operating field bias generated by the application of an operating voltage. The change in the field bias exposes the dielectric to a similar dynamic stress that microelectronic devices ordinarily experience. At the operating field stage, a gate current is measured and compared to a predetermined range. Once the gate current exceeds that range the test concludes. Otherwise, the test cycles between the above-mentioned phases for a predetermined number of iterations based on prior experimental correlation. In a destructive testing mode, the process is continuous and does not conclude until the gate current exceeds a predetermined range. The ultra-thin dielectric gate current may also be measured as the ultra-thin dielectric is heated so that the transport properties or reliability of the ultra-thin dielectric is more clearly understood.

Method for quantifying ultra-thin dielectric reliability: time dependent

A method for fabricating metal lines in multilevel VLSI semiconductor integrated circuit devices is provided so as to reduce parasitic capacitance. An undercutting etching step is performed so as to form trenches underneath the metal lines for accommodating air voids, followed by forming an intra-layer dielectric between the metal lines and into the trenches so as to form air voids underneath the metal lines. As a result, the parasitic capacitance will be decreased.

Air voids underneath metal lines to reduce parasitic capacitance

An interconnect structure capable of reducing intralevel capacitance in a damascene metalization process employs entrapped air gaps between metal lines. The structure comprises at least first and second metal regions separated by a dielectric region, an air gap formed at least partially within the dielectric region, a diffusion barrier positioned over the two metal regions covering a portion of the upper surface of the air gap, and an insulating layer positioned over the diffusion barrier sealing the upper surface of the air gap.

Semiconductor interconnect structure with air gap for reducing

A collimator system for use in PVD sputtering of semiconductor wafers having multiple tiers provided between a target and wafer substrate. The collimator system prevents target atoms from contacting the wafer at substantially oblique angles, thereby providing good step coverage uniformity over the surface of the wafer. Additionally, the presence of more than one tier prevents localized build-up of target atoms that occurs in conventional single tier collimators, thereby providing good flat coverage uniformity over the surface of the wafer.

Multiple tier collimator system for enhanced step coverage and uniformity

A PVD sputter system having a nonplanar target surface is disclosed. The configuration of the nonplanar target surface is adjusted to provide improved uniformity in deposition film thickness and step coverage at the peripheral boundary regions of the substrate. Emission-inducing power is distributed independently to different portions of the nonplanar target surface so as to modify the deposition profile according to substrate size and other factors.

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Palo Alto, CA, United States of America

David S Bang