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Micro Crystal Ag

Csem Centre Suisse D'electronique Et De Microtechnique Sa-Recherche Et Dévelopment

Rolex Sa

Csem Centre Suisse D'electronique Et De

Csem Centre Suisse D'electronique Et De Microtechique Sa, Recherche Et Developpement

Csem, Centre Suisse D'electronique Et Microtechnique Sa

Csem Centre Suisse D'electronique Et De Microtechnique Sa

David Ruffieux

Nicola Scolari

Alain-Serge Porret

Jacques Haesler

Claude Bourgeois

Steve Lecomte

Laurent Balet

Marc Pon Sole

Camilo Andres Salazar Gutierrez

Marc Pons Sole

Daniel Severac

Jean-Luc Nagel

Jacek Baborowski

Marc-Alexandre Dubois

Marc Pon SolÉ

An electronic device including a digital circuit to be compensated and a compensation device for compensating PVT variations of this digital circuit. This compensation device is arranged also for controlling the operating speed of the digital circuit and can also be arranged for equalising a rise time and a fall time of a logic gate including the transistors of the digital circuit. The electronic device implements a first loop, allowing to control the operating speed of the digital circuit by exploiting the same voltage at the compensation terminals of the compensation device and at the terminals at the digital circuit and at a critical path replica module allowing to control the threshold voltages of the respective transistors. The electronic device can implement also a second loop allowing to equalise the rise and fall times of a logic gate including the transistors of the digital circuit.

Electronic device

A compensation device for compensating PVT variations of an analog and/or digital circuit. The compensation device includes a transistor having a first terminal, a second terminal, a third terminal, and a fourth terminal allowing to modify a threshold voltage of the transistor. The transistor is configured to be in saturation region. The voltage at the third terminal has a predetermined value and the difference between the voltage at the second terminal and the voltage at the third terminal has a predetermined value. A current generation module is configured to generate a current of a predetermined value. A compensation module is configured to force this current to flow between the first terminal and the third terminal by adjusting the voltage of the fourth terminal.

Compensation device for compensating PVT variations of an analog and/or digital circuit

A wristwatch, which comprises an atomic oscillator comprising a system for detecting the beat frequencies obtained by the Raman effect.

Wristwatch with atomic oscillator

The temperature compensated timing signal generator comprises a crystal oscillator that generates a reference time signal, and a divider circuit that receives the reference time signal as input and outputs a coarse time unit signal, the coarse time unit signal having an actual frequency deviating from a desired frequency as a function of temperature of the crystal oscillator. The signal generator also includes a high frequency oscillator configured to generate an interpolation signal having a frequency greater than the frequency of the crystal oscillator. A finite state machine computes a deviation compensating signal as a function of temperature, the signal comprises an integer part representative of an integer number of pulses to be inhibited or injected in the divider circuit and a fractional part representative of how much the output of a new time unit signal pulse should further be delayed to compensate for any remaining deviation.

Temperature compensated timing signal generator

The temperature compensated timing signal generator comprises a crystal oscillator that generates a reference time signal, and a divider circuit that receives the reference time signal as input and outputs a coarse time unit signal, the coarse time unit signal having an actual frequency deviating from a desired frequency as a function of temperature of the crystal oscillator. The signal generator also includes a high frequency oscillator that generates an interpolation signal having a frequency greater than the frequency of the crystal oscillator. A finite state machine computes a deviation compensating signal as a function of the temperature signal, the signal comprises an integer part representative of an integer number of pulses to be inhibited or injected in the divider circuit and a fractional part representative of how much the output of a new time unit signal pulse should further be delayed to compensate for any remaining deviation.

A frequency synthesizer includes: a first oscillator () controlled by a first control device, the first oscillator having a high quality factor that is greater than 300 and produces a first clock signal () RF having a fixed frequency, the first control device () controlling the frequency of the first controlled oscillator () on the basis of a first reference frequency; a second oscillator () controlled by a second control device and producing a second clock signal (); the second control device () controlling the frequency of the second controlled oscillator () on the basis of a second reference frequency; and an integer frequency divider () dividing the frequency of the second clock signal () by a variable integer factor Nand producing a third clock signal (), the frequency of which is continuously variable by modifying the factor Nand the control of the second oscillator.

Frequency synthesizer

A device for compensating for the frequency of a resonator includes (a) a temperature sensor, (b) a sequencer determining a second compensation signal on the basis of the temperature and corresponding to a positive value N, and a third compensation signal on the basis of the temperature corresponding to a ratio between a positive integer S and N, S being lower than or equal to N, and (c) a variable counter receiving the compensation signals and generating a fourth output signal every N periods of a clock signal from the resonator and generating a fifth signal for modifying the charge capacity of the resonator.

Device and method for compensating for a resonator

The invention relates to a silicon resonator () of the tuning-fork type in which the linear frequency drift depending on the temperature is compensated. The resonator includes a silicon base (), a plurality of parallel arms () capable of vibrating and actuator (), wherein the arms include a silicon layer provided between two layers of silicon oxide having a thickness, relative to that of the silicon layer, such that it ensures the first-order compensation of the resonator thermal drift.

Silicon resonator of the tuning-fork type

Phase-locked loop

This clock generator comprises an oscillator for generating an alternating current pilot signal and a pulse formatting circuit which is intended to convert the pilot signal from the oscillator into a pulse clock signal having a duty factor of at least approximately 50%. According to one implementation, a series of at least two inverters is provided, the input of the first inverter being controlled by the alternating current pilot signal and the output of the second inverter supplying the clock signal. A power supply means may also be provided to supply the inverters with a regulated power supply voltage dependent on the signals appearing at the outputs of the inverters.

Clock generator

A differential oscillator circuit including first () and second () branches each including the series arrangement, between high (VDD) and low (VSS) supply potentials, of a transistor () and bias means () for imposing a determined current through the current terminals of the transistor. The transistors are interconnected so as to form a crossed pair of transistors, the most positive current terminal of each transistor (on the 'drain' side) being connected to the control terminal of the other transistor of the crossed pair. This differential oscillator circuit further includes an electro-mechanical resonator () connected to the crossed transistor pair on the 'drain' side, as well as a capacitive element () connected to the crossed transistor pair on the &#x201c;source&#x201d; side. The capacitance value of the capacitive element is selected so as to be less than a maximum value above which relaxation of the oscillator circuit can occur and thereby prevent relaxation of the oscillator circuit.

Differential oscillator circuit including an electro-mechanical resonator

The voltage controlled oscillator circuit includes a resonant circuit, with two inductive elements (LL) and a variable capacitive element (C), which is connected to a high potential terminal (V) of a voltage source, and a pair of cross-coupled NMOS transistors (NN), which is connected between two oscillating signal (V, V) output terminals of the resonant circuit. Each NMOS transistor of the pair is connected in parallel to a diode mounted NMOS transistor (NN) so as to form a current mirror. An identical current is supplied to each diode mounted transistor in an oscillating signal amplitude regulation loop. Two resistors (RR) series connected between the gates of the transistors of the pair (NN) allow extraction of the common mode voltage to be stored in a filtering capacitor (Cm) in order to bias a reference NMOS transistor (N) connected to a reference resistor (R). The current value supplied to the diode mounted transistors is dependent upon the value of the resistor and the detected common mode voltage. Consequently, the common mode voltage decreases with an increase in the oscillating signal amplitude, and vice versa. This oscillator circuit can be used in a low power electronic device, such as a portable telephone or a watch.

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Lugnorre, Switzerland

David Ruffieux