Advanced Micro Devices Corporation

Ati Technologies Ulc

David Ronald Oldcorn

Matthäus G Chajdas

Steven J Tovey

Michael A Kern

Skyler Jonathon Saleh

Timour T Paltashev

Raja Koduri

Andrew S Pomianowski

Brian K Bennett

Michael John Livesley

Daniel James Skinner

David William John Pankratz

Zhuo Chen

Qun Lin

David Kirk Mcallister

Zhou Chen

Amit Ben-Moshe

A technique for performing ray tracing operations is provided. The technique includes identifying triangles to include in a compressed triangle block; storing data common to the identified triangles as common data of the compressed triangle block; and storing data unique to the identified triangles as unique data of the compressed triangle block.

Bounding volume hierarchy leaf node compression

Described herein are techniques for reducing divergence of control flow in a single-instruction-multiple-data processor. The method includes, at a point of divergent control flow, identifying control flow targets for different execution items, sorting the execution items based on the control flow targets, reorganizing the execution items based on the sorting, and executing after the point of divergent control flow, with the reorganized execution items.

Compute unit sorting for reduced divergence

Systems, apparatuses, and methods for implementing graphics pipeline optimizations are disclosed. A user interface (UI) is generated to allow a user to analyze shaders and determine resource utilization on any of multiple different target graphic devices. The UI allows the user to manipulate the state associated with the target graphics device for a given graphics pipeline. After being edited by the user, the state of the graphics pipeline is converted into a textual representation and input into a meta-app. The meta-app creates an application programming interface (API) construct from the shader source code and textual representation of the state which is compiled by a driver component into machine-level instructions. Also, resource usage statistics are generated for a simulated run of the graphics pipeline on the target graphics device. Then, the machine-level instructions and resource usage statistics are displayed in the UI for the user to analyze.

Graphics pipeline optimizations

Described herein is a technique for performing operations for a bounding volume hierarchy. The techniques include: for a bounding box with quantized orientation, the bounding box being part of a bounding volume hierarchy, rotating a ray according to the quantized orientation to generate a rotated ray; performing an intersection test against the bounding box with the rotated ray; and according to the results of the intersection test, continuing traversal of the bounding volume hierarchy.

Bounding volume hierarchy having oriented bounding boxes with quantized rotations

Described herein is a technique for modifying a bounding volume hierarchy. The techniques include combining preferred orientations of child nodes of a first bounding box node to generate a first preferred orientation; based on the first preferred orientation, converting one or more child nodes of the first bounding box node into one or more oriented bounding box nodes; combining preferred orientations of child nodes of a second bounding box node to generate a second preferred orientation; and based on the second preferred orientation, maintaining one or more children of the second bounding box node as non-oriented bounding box nodes.

Techniques for introducing oriented bounding boxes into bounding volume hierarchy

Techniques for scheduling operations for a task graph on a processing device are provided. The techniques include receiving a task graph that specifies one or more passes, one or more resources, and one or more directed edges between passes and resources; identifying independent passes and dependent passes of the task graph; based on performance criteria of the processing device, scheduling commands to execute the passes; and transmitting scheduled commands to the processing device for execution as scheduled.

Task graph scheduling for workload processing

Techniques for generating a task graph for workload scheduling based on a task graph specification program are provided. The techniques include executing control flow instructions of the task graph specification program to traverse the task graph specification program; generating pass nodes of the task graph based on pass instructions of the task graph specification program; generating resource nodes and directed edges based on resource declarations of the task graph specification program; and outputting the task graph specification program to a command scheduler for scheduling.

Task graph generation for workload processing

Described herein are techniques for reducing control flow divergence. The method includes identifying two or more shader programs having commonalities, generating a merged shader program that implements functionality of the identified two or more shader programs, wherein the functionality implemented includes a first execution option for a first shader program of the two or more shader programs and a second execution option for a second shader program of the two or more shader programs, modifying shader programs that call the first shader program to instead call the merged shader program and select the first execution option, modifying shader programs that call the second shader program to instead call the merged shader program and select the second execution option.

Shader merge for reduced divergence

A system and method for allocating commands in processing is disclosed. The system and method includes an application running on a computer system that provides commands to be executed on one of a plurality of processors capable of executing the commands, the commands provided through an application programming interface, a device driver that buffers the streamed commands and converts the streamed commands into a format used by a GPU, and an operating system that builds a command buffer by grouping a plurality of converted commands based on an allocation for an available processor, wherein the available processor is determined in the interface between the device driver and the operating system. The available processor is one of the plurality of processors capable of executing the commands that receives the command buffer from the operating system, queues the command buffer and performs an asynchronous submission of the command buffer to the GPU, and the GPU executes the command buffer.

Asynchronous submission of commands

The present invention provides an analysis method that uses error metrics to determine whether an image is suitable for compression. One embodiment of the present invention can make the determination in real-time. In one embodiment, analysis methods based on four error metrics are used to determine whether a compressed image should be used. The first metric is a signal-to-noise (SNR) error metric that prevents compressed images with low SNR from being used to represent original images. Another metric is detecting the geometric correlation of pixels within individual blocks of the compressed images. The third metric is used to determine whether color mapping in the compressed images are well-mapped. A final metric is a size metric that filters images smaller than a certain size and prevents them from being compressed. As most analysis methods are integral parts of the compression process, the present invention incurs little cost collecting error metric data.

Growing community of inventors

Milton Keynes, United Kingdom

David Ronald Oldcorn