Cypress Semiconductor Corporation

Camgian Microsystems Corp.

David Robert Lindley

Jeffery Scott Hunt

Muthukumar Nagarajan

Derrick J Savage

Gary Butler

Andrew L Hawkins

George M Ansel

Junfei Fan

Jeffrey W Gossett

Michael D Carlson

Jun Li

Michael David Fliesler

William G Baker

Morgan Andrew Whately

Vinod Rajan

The present invention relates generally to a system and method of networking and interconnecting a large number of various types of sensors to a remote location in an efficient manner Specifically, the invention utilizes a flexible, configurable, scalable and power-efficient sensor interface relay architecture to gather sensor data from various locations and then relay it to a remote location via the internet.

Multiple sensor data processor interface and relay

The present invention relates generally to a system and method of networking and interconnecting a large number of various types of sensors to a remote location in an efficient manner. Specifically, the invention utilizes a flexible, configurable, scalable and power-efficient sensor interface relay architecture to gather sensor data from various locations and then relay it to a remote location via the internet.

Disclosed is a dynamic detector to detect an environmental condition including a power-supply level relative to a predetermined threshold signal during a training phase; and an adjustable buffer, coupled with the dynamic detector, configured to adjust output drive strength during the training phase in response to the detected environmental condition.

Method and apparatus for dynamically detecting environmental conditions and adjusting drive strength in response to the detecting

A memory having a circuit including a built-in address counter with a test mode. The address counter may be used to generate the memory array addressing for the different array test patterns. The circuit may comprise a logic circuit and a counter circuit. The logic circuit may be configured to generate one or more control signals in response to one or more control inputs. The counter circuit may be configured to generate a first counter output and a second counter output in response to (i) the control outputs and (ii) one or more inputs. The counter may comprise a first portion configured to generate the first counter output and a second portion configured to generate the second counter output.

Address counter test mode for memory device

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first output signal in response to one or more first input signals. The second circuit may be configured to generate a second output signal in response to one or more second input signals. The first and second output signals may be presented to a bond pad.

Electrical ID method for output driver

A method and means for use when doing multiple products on an IC die and it becomes necessary to no-bond a control or address input thus requiring the connection of this IC input to a voltage of the proper polarity. In such a situation, an unused input pad is selectively bonded to a supply leadframe finger and connected to suitable logic to pull the unconnected IC input to the proper voltage. An embodiment whereby problems with noisy input voltages can be readily overcome is also described.

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Starkville, MS, United States of America

David Robert Lindley