Ati International Srl

Emc Corporation

Ati Technologies Ulc

Emc IP Holding Company LLC

Ati Technologies Inc.

David Reese

John S Yates, Jr

Korbin S Van Dyke

Paul Henry Hohensee

Steven T McClure

T R Ramesh

Stephen C Purcell

Shalesh Thusoo

Steven R Chalmer

Niteen Aravind Patkar

Gurjeet Singh Saund

Tiruvur R Ramesh

Brett D Niver

John Forecast

Michael C Adler

Matthew H Fredette

Serge Joseph Pirotte

Clifford Lim

Steve Chalmer

Louis Krigovski

A data storage system includes compute engines each including a CPU complex, physical memory, interfaces to host computers and physical storage devices, and a fabric interface. A non-cache-coherent fabric interconnects the compute engines as cluster members of a cluster, the fabric supporting a global lock enabling each cluster member to obtain temporary exclusive access to addressable units of non-virtual memory. The CPU complexes implement a global virtual memory (GVM) on top of the non-virtual memory, including (1) a globally shared GVM page table of global page table entries, each identifying the cluster members having a corresponding GVM page mapped, and (2) GVM page management functionality including (i) use of the global lock to obtain exclusive access to the global page table entries for page management operations, and (ii) transfer of underlying data of the pages of the GVM among the cluster members.

Data storage system with cluster virtual memory on non-cache-coherent cluster interconnect

Operating at least one hypervisor includes running a first hypervisor as a first thread of an underlying operating system, running a second hypervisor as a second thread of the underlying operating system, loading a first guest operating system using the first hypervisor based on the first thread of the underlying operating system, loading a second guest operating system using the second hypervisor based on the second thread of the underlying operating system, and scheduling sharing of resources of the underlying system between the first hypervisor and the second hypervisor according to a scheduler of the underlying operating system, where the first hypervisor and the second hypervisor run independently of each other. The scheduler of the underlying operating system may schedule fractional time shares for the first hypervisor and the second hypervisor to access the same resource.

Extended fractional symmetric multi-processing capabilities to guest operating systems

Methods and systems are disclosed that relate to running a plurality of software instances on an embedded computer system without requiring substantial modifications to each software instance. An exemplary method includes storing context information relating to a first instance. An instance includes a set of independent threads of execution each with its own code context, interrupt service routines, drivers, and operating system services. Both a second instance and a thread associated with the second instance are chosen to run. Context information relating to the second instance is restored and the second instance is run on the operating system.

Methods and systems for allocating hardware resources to instances of software images

Methods and systems are disclosed that relate to handling interrupts across multiple software instances. An exemplary method includes receiving an interrupt at a current CPU. An instance includes a set of independent threads of execution each with its own code context, interrupt service routines, drivers, and operating system services. The method further includes storing context information relating to the first instance, identifying the second instance associated with the interrupt, running at least one interrupt service routine, and restoring the context information relating to the first instance.

Methods and systems for handling interrupts across software instances and context switching between instances having interrupt service routine registered to handle the interrupt

A computer has instruction pipeline circuitry capable of executing two instruction set architectures (ISA's). A binary translator translates at least a selected portion of a computer program from a lower-performance one of the ISA's to a higher-performance one of the ISA's. Hardware initiates a query when about to execute a program region coded in the lower-performance ISA, to determine whether a higher-performance translation exists. If so, the about-to-be-executed instruction is aborted, and control transfers to the higher-performance translation. After execution of the higher-performance translation, execution of the lower-performance region is reestablished at a point downstream from the aborted instruction, in a context logically equivalent to that which would have prevailed had the code of the lower-performance region been allowed to proceed.

Detecting conditions for transfer of execution from one computer instruction stream to another and executing transfer on satisfaction of the conditions

A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page.

Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code

A microprocessor chip has instruction pipeline circuitry, and instruction classification circuitry that classifies instructions as they are executed into a small number of classes and records a classification code value. An on-chip table has entries corresponding to a range of addresses of a memory and designed to hold a statistical assessment of a value of consulting an off-chip table in a memory of the computer. Lookup circuitry is designed to fetch an entry from the on-chip table as part of the basic instruction processing cycle of the microprocessor. A mask has a value set at least in part by a timer. The instruction pipeline circuitry is controlled based on the value of the on-chip table entry corresponding to the address of instructions processed, the current value of the mask, the recorded classification code, and the off-chip table.

Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor

Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination

Managing memory includes receiving a request for a memory allocation, determining whether the memory allocation is to be maintained when subsequently initializing memory and saving information about the memory allocation to maintain the memory allocation during subsequently initializing memory. Initializing may be performed as part of special reset mode processing. Special reset mode processing may be performed in response to receiving a reset command. The memory may be shared by a plurality of processing units and the reset command may be issued to reset a first processing unit causing reset of the memory and a second processing unit may use a first allocated memory portion that is maintained when initializing the memory as part of processing for the reset command. Saving may include adding an entry to an allocation list associated with the memory, the entry including a location associated with the memory allocation.

Generic reallocation function for heap reconstitution in a multi-processor shared memory environment

A computer binary translator translates at least a segment of a binary representation of a program from a first instruction set architecture to a second instruction set architecture. A sequence of side-effects in the translation differs from a sequence of side-effects in the original. The translation distinguishes memory loads that are believed to be directed to well-behaved memory from memory loads that are believed to be directed to non-well-behaved memory device(s). Instruction execution circuitry identifies a memory reference that has a side-effect that has been reordered by translation, the memory reference having been believed at translation time to be directed to well-behaved memory but at execution it is found that the reference cannot be guaranteed to be well-behaved. The instruction execution circuitry identifies whether the difference in side-effect order may have a material effect on the execution of the program. A roll-back program state is established, and execution of the original code resumes.

Detecting reordered side-effects

Profiling execution of a program. The program is coded in a mode-dependent instruction set. During a profile-quiescent execution interval, the profile circuitry records no profile information. After a triggering event is detected, the profile circuitry commences a profiled execution interval, and records profile information describing every profileable event during that interval. The profiled information includes at least all divergence of execution from sequential execution and processor mode changes not inferable from instruction opcode. The recorded profile information is efficiently tailored to annotate the profiled binary code with sufficient processor mode information to resolve mode-dependency, and indicates contiguous ranges of sequential instructions executed during a profiled interval by low and high boundaries of the contiguous ranges, indicating the high boundary by the address of the last byte. The profile information identifies each distinct physical page of instruction text executed during the interval.

Profiling ranges of execution of a computer program

A method and a computer with circuitry configured for performance of the method are disclosed. During a profiled interval of an execution of a program on a computer, profile information is recorded describing the execution, without the program having been compiled for profiled execution. The program is coded in an instruction set in which an interpretation of an instruction depends on a processor mode not expressed in the binary representation of the instruction. The recorded profile information describes at least all events occurring during the profiled execution interval of the two classes: (1) a divergence of execution from sequential execution; and (2) a processor mode change that is not inferable from the opcode of the instruction that induces the processor mode change taken together with a processor mode before the mode change instruction. The profile information further identifies each distinct physical page of instruction text executed during the execution interval.

Profiling program execution to identify frequently-executed portions and to assist binary translation

A microprocessor chip, and methods for use in that microprocessor chip. The chip has instruction pipeline circuitry and address translation circuitry. Table lookup circuitry indexes into a table, the table having an entry associated with each corresponding address range translated by the address translation circuitry. Each entry of the table describes a likelihood of the existence of an alternate coding of instructions located in the respective corresponding address range. The table lookup circuitry retrieves a table entry corresponding to the address, and is operable as part of the basic instruction cycle of executing an instruction of a non-supervisor mode program executing on a computer. Interrupt circuitry is cooperatively designed with the instruction pipeline circuitry to trigger an interrupt on execution of an instruction of a process, synchronously based at least in part on a memory state of the computer and the address of the instruction, the architectural definition of the instruction not calling for an interrupt. A handler for the interrupt is responsive to the contents of the table to affect the instruction pipeline circuitry to effect control of an architecturally-visible data manipulation behavior or control transfer behavior of the instruction based on the contents of a table entry associated with the instruction.

Side tables annotating an instruction stream

A method and a computer for performance of the method. While executing a program on a computer, profileable events occurring in the instruction pipeline are detected. The instruction pipeline is directed to record profile information describing the profileable events essentially concurrently with the occurrence of the profileable events. The detecting and recording occur under control of hardware of the computer without software intervention.

Profiling execution of computer programs

A computer having an instruction pipeline and profile circuitry. The profile circuitry detects and records, without compiler assistance for execution profiling, profile information describing a sequence of events occurring in the instruction pipeline. The sequence includes every event occurring during a profiled execution interval that matches time-independent selection criteria of events to be profiled. The recording continues until a predetermined stop condition is reached. The profile circuitry detects the occurrence of a predetermined condition, after a non-profiled interval of execution, and then commences the profiled execution interval.

Profiling execution of a sequence of events occuring during a profiled execution interval that matches time-independent selection criteria of events to be profiled

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Westborough, MA, United States of America

David Reese